search for: splatvector

...onstants instead of intrinsics) relies quite heavily on this > for good code generation, so we will need to find new ways to recognize and > fold these values. > > ================== > 5. Code Generation > ================== > > IR splats will be converted to an experimental splatvector intrinsic in > SelectionDAGBuilder. > > All three intrinsics are custom lowered and legalized in the AArch64 backend. > > Two new AArch64ISD nodes have been added to represent the same concepts > at the SelectionDAG level, while splatvector maps onto the existing > AArch64ISD::...

...<scalable 2 x i64> %sv1 > %res2 = shufflevector <scalable 4 x double> %in, <scalable 4 x double> undef, <scalable 2 x i64> %sv2 > `` > > ================== > 6. Code Generation > ================== > > IR splats will be converted to an experimental splatvector intrinsic in > SelectionDAGBuilder. > > All three intrinsics are custom lowered and legalized in the AArch64 backend. > > Two new AArch64ISD nodes have been added to represent the same concepts > at the SelectionDAG level, while splatvector maps onto the existing > AArch64ISD...

...ding. Our downstream compiler (using Constants instead of intrinsics) relies quite heavily on this for good code generation, so we will need to find new ways to recognize and fold these values. ================== 5. Code Generation ================== IR splats will be converted to an experimental splatvector intrinsic in SelectionDAGBuilder. All three intrinsics are custom lowered and legalized in the AArch64 backend. Two new AArch64ISD nodes have been added to represent the same concepts at the SelectionDAG level, while splatvector maps onto the existing AArch64ISD::DUP. GlobalISel ---------- Sinc...

...ding. Our downstream compiler (using Constants instead of intrinsics) relies quite heavily on this for good code generation, so we will need to find new ways to recognize and fold these values. ================== 5. Code Generation ================== IR splats will be converted to an experimental splatvector intrinsic in SelectionDAGBuilder. All three intrinsics are custom lowered and legalized in the AArch64 backend. Two new AArch64ISD nodes have been added to represent the same concepts at the SelectionDAG level, while splatvector maps onto the existing AArch64ISD::DUP. GlobalISel ---------- Sinc...

...ding. Our downstream compiler (using Constants instead of intrinsics) relies quite heavily on this for good code generation, so we will need to find new ways to recognize and fold these values. ================== 5. Code Generation ================== IR splats will be converted to an experimental splatvector intrinsic in SelectionDAGBuilder. All three intrinsics are custom lowered and legalized in the AArch64 backend. Two new AArch64ISD nodes have been added to represent the same concepts at the SelectionDAG level, while splatvector maps onto the existing AArch64ISD::DUP. GlobalISel ---------- Sinc...

...onstants instead of intrinsics) relies quite heavily on this > for good code generation, so we will need to find new ways to recognize and > fold these values. > > ================== > 5. Code Generation > ================== > > IR splats will be converted to an experimental splatvector intrinsic in > SelectionDAGBuilder. > > All three intrinsics are custom lowered and legalized in the AArch64 backend. > > Two new AArch64ISD nodes have been added to represent the same concepts > at the SelectionDAG level, while splatvector maps onto the existing > AArch64ISD::...

...4 x double> %in, <scalable 4 x > double> undef, <scalable 2 x i64> %sv2 > > `` > > > > ================== > > 6. Code Generation > > ================== > > > > IR splats will be converted to an experimental splatvector > intrinsic in > > SelectionDAGBuilder. > > > > All three intrinsics are custom lowered and legalized in the > AArch64 backend. > > > > Two new AArch64ISD nodes have been added to represent the same > concepts > > at t...

...<scalable 2 x i64> %sv1 > %res2 = shufflevector <scalable 4 x double> %in, <scalable 4 x double> undef, <scalable 2 x i64> %sv2 > `` > > ================== > 6. Code Generation > ================== > > IR splats will be converted to an experimental splatvector intrinsic in > SelectionDAGBuilder. > > All three intrinsics are custom lowered and legalized in the AArch64 backend. > > Two new AArch64ISD nodes have been added to represent the same concepts > at the SelectionDAG level, while splatvector maps onto the existing > AArch64ISD::...

...he element type increases in size. If you want to extract something other than the first part of a vector, you need to add offsets based on a calculation from vscale (e.g. adding vscale * (min_elts/2) allows you to reach the high half of a larger register). If you check the patch which introduces splatvector (https://reviews.llvm.org/D47775), you can see a line which currently produces an error if changing the size of a vector is required, and notes that VECTOR_SHUFFLE_VAR hasn't been implemented yet. In our downstream compiler, this is an ISD alongside VECTOR_SHUFFLE which allows a shuffle with a...