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...how with a flag or by doing some code editing? Can you point me to which passes may do that? I'm working on editing a backend that can't work with anything larger than 32 bits. Does the legalize stage work on IR code? Maybe i can use that? On Jan 29, 2015 5:41 AM, Ruiling Song <ruiling.song83 at gmail.com> wrote: LLVM contains some optimization pass that will generate instructions operate on i64 or even i128 and more. The upstream backend utilize the legalize stage that can break it into instructions with smaller integer types if the target machine does not support that large integer...

...iminates too-wide integer types by decomposing the > operations. > > However, SROA never produces an integer wider than what was used in the > input IR that I know of... I would be surprised if GVN did this either. > > > On Wed, Sep 3, 2014 at 10:53 PM, Ruiling Song <ruiling.song83 at gmail.com> > wrote: > >> Hi, >> >> I am currently working on an opencl project based on LLVM, the target >> device is 32bit. >> I met a problem that some llvm passes like GVN SROA will generate some IR >> operating >> on wide integer types like...

...oing some code editing? Can you point me to which passes may do > that? > > I'm working on editing a backend that can't work with anything larger than > 32 bits. Does the legalize stage work on IR code? Maybe i can use that? > On Jan 29, 2015 5:41 AM, Ruiling Song <ruiling.song83 at gmail.com> wrote: > > LLVM contains some optimization pass that will generate instructions > operate on i64 or even i128 and more. The upstream backend utilize the > legalize stage that can break it into instructions with smaller integer > types if the target machine does not...

> On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote: > > > > 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net <mailto:tom at stellard.net>>: > > > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > > > Hi, > > > > > > I am working on a...

Hi, I am currently working on an opencl project based on LLVM, the target device is 32bit. I met a problem that some llvm passes like GVN SROA will generate some IR operating on wide integer types like i128 or i512. But the device does not support such kind of data type. Is there any idea on how to lower this kind of IR to only operate on i32 or vector of i32? Or is there any existing code handle

On Wed, Dec 21, 2016 at 10:31:57AM -0500, Matt Arsenault wrote: > > > On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote: > > > > > > > > 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net <mailto:tom at stellard.net>>: > > > > > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > > > > Hi, > > &g...

Hi Escha, Great to have your comment! Do you have any specific reason for not doing like this? I am not sure whether I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case, may be something like I only need to define r0~r127 as register for i32 register (each r#

2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net>: > > On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: > > Hi, > > > > I am working on a new LLVM target for Intel GPU, which also has same kind > > of scalar/vector register classes used in AMDGPU target. Like for a i32 > > virtual register, it will be held in scalar register if its

Hi, I want to get the information where the address of load/store comes from, like below load instruction, %152 may come from a getelementpr, or comes from some gep+ptrtoint+add+inttoptr... instructions. what's the recommended way to find the original memory pointer? %153 = load <2 x i16> addrspace(1)* %152, align 2 going through the use-def chain seems not easy, because the

...ribute? > Message-ID: > <CAAv59xRGZ_84MXN=69gBj=TZEfXBBMtHWiOyhzYZ7hV7_+JtOg at mail.gmail.com> > Content-Type: text/plain; charset="utf-8" > > 2016年12月21日星期三，Matt Arsenault <arsenm2 at gmail.com> 写道： >> On Dec 21, 2016, at 10:26, Ruiling Song <ruiling.song83 at gmail.com> wrote: >> >> >> 2016-12-20 22:14 GMT+08:00 Tom Stellard <tom at stellard.net>: >>> On Tue, Dec 20, 2016 at 11:00:09AM +0800, Ruiling Song wrote: >>>> Hi, >>>> >>>> I am working on a new LLVM target for Intel GPU,...

...(if your SIMD width is 16) VGPR 20 overlaps SGPR 320, > 321….335. So you can have 128 vector registers, 16*128 uniforms, or a mix > of the two. > > (Maybe some of the AMDGPU maintainers have thoughts?) > > —escha > > > On Aug 22, 2016, at 8:07 PM, Ruiling Song <ruiling.song83 at gmail.com> > wrote: > > Hi Escha, > > Great to have your comment! Do you have any specific reason for not doing > like this? > I am not sure whether I understand your point correctly. For "just model > one thread", > do you mean "only considering ONE...