search for: smalen

...that allows us to better coordinate our efforts and to have a collated list of open SVE/SVE2 patches on Phabricator. I'll try to keep this list up-to-date! https://docs.google.com/document/d/1ph1l1KhrrHgBlrKeEnuoIPrVO9jTjHvcwUlz61QWNMA Cheers, Sander > On 5 Dec 2019, at 22:44, Sander De Smalen <Sander.DeSmalen at arm.com> wrote: > > Thanks to everyone who filled in the Doodle poll! > > The first SVE/SVE2 LLVM sync-up call will be held on: > Thursday 12 Dec, 4pm GMT / 8am PST > > Please add your name and email address to the document linked below, so I can f...

...pple.com> wrote: > > I’m fine with the direction this is going, but let’s keep renaming to a minimum. They’ve been experimental long enough now that we should be able to now jump to a final form after all the feedback. > > Amara > >> On Apr 10, 2019, at 5:59 AM, Sander De Smalen via llvm-dev <llvm-dev at lists.llvm.org> wrote: >> >>> >>> On 8 Apr 2019, at 11:37, Simon Moll <moll at cs.uni-saarland.de> wrote: >>> >>> Hi, >>> >>> On 4/5/19 10:47 AM, Simon Pilgrim via llvm-dev wrote: >>>>...

Hi all, Several people have expressed interest in having regular sync-up calls to follow the progress of ARM SVE/SVE2 support in LLVM. With this effort picking up steam and multiple people contributing patches, regular sync-up calls would provide a platform to coordinate our efforts. Items to discuss in these sync-up calls would include: - SVE/SVE2 CodeGen support - Adding support for C/C++

...; Sent: 19 May 2020 09:56 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication Hi Sjoerd, On 5/18/20 3:43 PM, Sjoerd Meijer wrote: > You have similar problems with https://reviews.llvm.org/D79100 The new revision D79100<https://revie...

...; Sent: 18 May 2020 14:11 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/18/20 2:53 PM, Sjoerd Meijer wrote: Hi, I abandoned that approach and followed Eli's suggestion, see somewhere earlier in this thread, and emit an intrin...

...; Sent: 19 May 2020 15:07 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/19/20 12:38 PM, Sjoerd Meijer wrote: Hi Simon, Thanks for reposting the example, and looking at it more carefully, I think it is very similar to my first pr...

Hello, Just bringing to people's attention that we organise a bi-weekly sync-up call to discuss and collaborate on upstream support for scalable vectors and SVE/SVE2 CodeGen support in LLVM. The meetings are held every other Thursday, with the next meeting tomorrow (April 2nd) at 3pm GMT / 7am PST. The invite and agenda for tomorrow's meeting (including links to minutes from previous

...s would explain the FileCheck output from those failing tests. Could there be a buildbot misconfiguration which is preventing the newly-built llvm-tblgen from being used? Oliver From: Galina Kistanova [mailto:gkistanova at gmail.com] Sent: 04 December 2017 22:30 To: Oliver Stannard Cc: Sander De Smalen; nd Subject: Re: buildbot failure in LLVM on llvm-clang-x86_64-expensive-checks-win Hi Oliver, I have requested a clean build of that exact revision and all the tests passes. http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/6561 This is kind of bad, as it seems som...

...; Sent: 18 May 2020 13:32 To: Sjoerd Meijer <Sjoerd.Meijer at arm.com> Cc: Roger Ferrer Ibáñez <rofirrim at gmail.com>; Eli Friedman <efriedma at quicinc.com>; listmail at philipreames.com <listmail at philipreames.com>; llvm-dev <llvm-dev at lists.llvm.org>; Sander De Smalen <Sander.DeSmalen at arm.com>; hanna.kruppe at gmail.com <hanna.kruppe at gmail.com> Subject: Re: [llvm-dev] LV: predication On 5/5/20 12:07 AM, Sjoerd Meijer via llvm-dev wrote: what we would like to generate is a vector loop with implicit predication, which works by setting up the the...

...Clang/LLVM. Thanks, JinGu Kang ________________________________ From: Graham Hunter <Graham.Hunter at arm.com> Sent: 28 May 2019 10:46 To: JinGu Kang Cc: Joel Jones; Chris Lattner; Hal Finkel; Jones, Joel; dag at cray.com; Renato Golin; Kristof Beyls; Amara Emerson; Florian Hahn; Sander De Smalen; Robin Kruppe; llvm-dev at lists.llvm.org; mkuper at google.com; Sjoerd Meijer; Sam Parker; nd Subject: Re: [EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths Hi JinGu, > Above vectorized loop does not need tail loop. I guess we could map the %mask.vec to predic...

Hi all, While working on a patch to improve codegen for fadd reductions on AArch64, I stumbled upon an outstanding issue with the experimental.vector.reduce.fadd/fmul intrinsics where the accumulator argument is ignored when fast-math is set on the intrinsic call. This behaviour is described in the LangRef (https://www.llvm.org/docs/LangRef.html#id1905) and is mentioned in

> On 8 Apr 2019, at 11:37, Simon Moll <moll at cs.uni-saarland.de> wrote: > > Hi, > > On 4/5/19 10:47 AM, Simon Pilgrim via llvm-dev wrote: >> On 05/04/2019 09:37, Simon Pilgrim via llvm-dev wrote: >>> On 04/04/2019 14:11, Sander De Smalen wrote: >>>> Proposed change: >>>> ---------------------------- >>>> In this RFC I propose changing the intrinsics for llvm.experimental.vector.reduce.fadd and llvm.experimental.vector.reduce.fmul (see options A and B). I also propose renaming the 'accumulator...

...;; Stotzer, Eric <estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkuper at google.com>; Caballero, Diego <diego.caballero at intel.com>; Sanjay Patel <spatel at rotateright.com>; Simon Pilgrim <ll...

...that, I also wanted to inform about the series of patches that I’ll be putting on Phabricator the coming months with some pointers to the SVE spec (for reference). Sander On 19/10/2017, 14:44, "Alex Bradbury" <asb at lowrisc.org> wrote: On 19 October 2017 at 05:12, Sander De Smalen via llvm-dev <llvm-dev at lists.llvm.org> wrote: > Hi, > > > > Probably a lot of you are attending interesting talks at LLVM Dev meeting > this week, so I hope this message isn't completely lost in all the > excitement. > &gt...

On 05/04/2019 09:37, Simon Pilgrim via llvm-dev wrote: > On 04/04/2019 14:11, Sander De Smalen wrote: >> Proposed change: >> >> ---------------------------- >> >> In this RFC I propose changing the intrinsics for >> llvm.experimental.vector.reduce.fadd and >> llvm.experimental.vector.reduce.fmul (see options A and B). I also >> propose renam...

I've posted two patches on Phabricator to add support for VScale in LLVM. A brief recap on `vscale`: The scalable vector type in LLVM IR is defined as `<vscale x n x m>`, to create types such as `<vscale x 16 x i8>` for a scalable vector with at least 16 bytes. In the definition of the scalable type, `vscale` is specified as a positive constant of type integer that will only be

...____ From: llvm-dev <llvm-dev-bounces at lists.llvm.org> on behalf of JinGu Kang via llvm-dev <llvm-dev at lists.llvm.org> Sent: 24 May 2019 21:47 To: Joel Jones; Chris Lattner; Hal Finkel; Jones, Joel; dag at cray.com; Renato Golin; Kristof Beyls; Amara Emerson; Florian Hahn; Sander De Smalen; Robin Kruppe; llvm-dev at lists.llvm.org; mkuper at google.com; Sjoerd Meijer; Sam Parker; Graham Hunter Cc: nd Subject: Re: [llvm-dev] [EXT] Re: [RFC][SVE] Supporting SIMD instruction sets with variable vector lengths Hi Joel, Thanks for your kind guide. > https://community.arm.com/develope...

...;; Stotzer, Eric <estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkuper at google.com>; Caballero, Diego <diego.caballero at intel.com>; Sanjay Patel <spatel at rotateright.com>; Simon Pilgrim <ll...

Hi, Probably a lot of you are attending interesting talks at LLVM Dev meeting this week, so I hope this message isn't completely lost in all the excitement. In the past month we have carved off our changes to LLVM's assembler/disassembler that implement the AArch64 SVE instruction set [1]. These changes are split these up into individual patches that purely focus on the assembler and

...;; Stotzer, Eric <estotzer at ti.com>; Nemanja Ivanovic <nemanja.i.ibm at gmail.com>; Kreitzer, David L <david.l.kreitzer at intel.com>; Nuzman, Dorit <dorit.nuzman at intel.com>; Adam Nemet <anemet at apple.com>; James Molloy <James.Molloy at arm.com>; Sander De Smalen <Sander.DeSmalen at arm.com>; Zaks, Ayal <ayal.zaks at intel.com>; Graham Hunter <Graham.Hunter at arm.com>; Michael Kuperstein <mkuper at google.com>; Caballero, Diego <diego.caballero at intel.com>; Sanjay Patel <spatel at rotateright.com>; Simon Pilgrim <ll...