search for: siregisterinfo

Yes, the arch is just as you said, something like AMD GPU, but Intel GPU don't have separate register file for 'scalar/vector'. In fact my idea of defining the register tuples was borrowed from SIRegisterInfo.td in AMD GPU. But seems that AMD GPU mainly support i32/i64 register type, while Intel GPU also support byte/short register type. So I have to start defining the registers from 'byte' type, and then build up other type registers through RegisterTuples. I thought RegisterTuple is kind of ex...

On Mon, Nov 4, 2019 at 12:18 PM Quentin Colombet <qcolombet at apple.com> wrote: > Hi Alex, > > Thanks for reporting this. > Wei worked on the hoisting optimization. > > @Wei, could you work with Alex to see what is the problem. > > Cheers, > -Quentin > > > On Nov 3, 2019, at 5:20 AM, via llvm-dev <llvm-dev at lists.llvm.org> > wrote: > >

Hi Escha, Great to have your comment! Do you have any specific reason for not doing like this? I am not sure whether I understand your point correctly. For "just model one thread", do you mean "only considering ONE of the 8/16 working lanes that running in lock-step way"?? For my case, may be something like I only need to define r0~r127 as register for i32 register (each r#

...get/AMDGPU/SIInstrInfo.td > llvm/trunk/lib/Target/AMDGPU/SIInstructions.td > llvm/trunk/lib/Target/AMDGPU/SIIntrinsics.td > llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp > llvm/trunk/lib/Target/AMDGPU/SIMachineFunctionInfo.h > llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.cpp > llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.h > llvm/trunk/lib/Target/AMDGPU/SIRegisterInfo.td > llvm/trunk/lib/Target/AMDGPU/SISchedule.td > llvm/trunk/lib/Target/AMDGPU/TargetInfo/ > llvm/trunk/lib/Target/AMDGPU/TargetInfo/AMDGPUTargetInfo.cpp > llv...