search for: registerinfo

Hello Everyone, I am trying to make a new LLVM backend target for Intel GPU. I would start from targeting OpenCL language first. But I am not quite familiar with LLVM backend infrastructure. I have some problem on describing the RegisterInfo. Intel GPU launches lots of hardware threads to do GPGPU workload. Each hardware thread has 128 registers(r0-r127), with each one of size 32 byte. Each hardware thread may run in SIMD 8/16/32 way, which maps to 8/16/32 OpenCL working items. And the SIMD width is chosen at compile time (normally ch...

...>> On 7/19/2017 4:47 PM, hameeza ahmed wrote: >> >> I have made changes in 3 files: >> LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are >> attached here. >> >> Now i am getting following errors. which means registerinfo.inc >> file is not generated successfully. >> >> /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: >> no member named 'XMM8' in namespace 'llvm::X86' >> if ((RegNo >= X86::XMM8 && RegN...

I have made changes in 3 files: LaneBitmask.h, codegenregisters.cpp and miparser.cpp. files are attached here. Now i am getting following errors. which means registerinfo.inc file is not generated successfully. /PIM/lib/Target/X86/MCTargetDesc/X86BaseInfo.h:733:24: error: no member named 'XMM8' in namespace 'llvm::X86' if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM31) || fatal error: too many errors emitted, stopping now [-fe...

Folks, Please confirm or correct the following assertions: In Target.td one of the data member fields for class Register is list<string> AltNames. If this is for alternate names for a given register (in Mips $28 and $gp are the same) it would be quite useful for the llvm-mc assembler which has to handle cases where there are multiple names for the same register. A quick recursive grep

Hi all, I just committed r183020 and r183061, that add Size/Offset information to SubRegIndex. If you maintain an out-of-tree target, there are a few things to change: - the SubRegIndex class has a new mandatory argument, representing the Size (in bits) covered by the index. If it's not meaningful (ex: same index for different kinds of registers), set it to -1 (though I believe this

On Tue, Sep 6, 2011 at 9:34 PM, Alexandru Dura <alexdura at gmail.com> wrote: > Hi everyone, > > I found some peculiar behavior of TableGen when generating > [TARGET]GenRegisterInfo.inc. Some register overlaps are generated twice in > this file, leading to a compilation error. Hi, What do you mean "overlapped register"? > I think this is because in RegisterInfoEmitter.cpp, RegisterAliases are > declared as "std::map<Record*, std::set<Record*...

...vm-dev at lists.llvm.org> wrote: > > Hello Everyone, > > I am trying to make a new LLVM backend target for Intel GPU. > I would start from targeting OpenCL language first. > But I am not quite familiar with LLVM backend infrastructure. > I have some problem on describing the RegisterInfo. > > Intel GPU launches lots of hardware threads to do GPGPU workload. > Each hardware thread has 128 registers(r0-r127), with each one of size 32 > byte. > Each hardware thread may run in SIMD 8/16/32 way, which maps to > 8/16/32 OpenCL working items. And the SIMD width is chosen...

..._N are treated separately. 1 will use Reg_B registers and other will use Reg_A respectively. Is it fine??? Please guide me... I need serious help, please..... Thank You On Mon, Jul 10, 2017 at 9:29 AM, hameeza ahmed <hahmed2305 at gmail.com> wrote: > or should i write a condition in registerinfo.td; to define the registers > in object Reg_A in specific order according to loop iterations. > > On Mon, Jul 10, 2017 at 9:17 AM, hameeza ahmed <hahmed2305 at gmail.com> > wrote: > >> hello, >> >> i have a situation where i have to assign the registers to ins...

...and would like our TargetLowering::LowerCall method to emit PUSH instructions (instead of STORE) to pass arguments (which would improve code density for function calls). Is there a way of keeping track of the stack pointer changes implied by the PUSH instruction to calculate the correct offsets in RegisterInfo::eliminateFrameIndex when the call sequence is generated ? Thanks a lot in advance, Rod

Hi everyone, I found some peculiar behavior of TableGen when generating [TARGET]GenRegisterInfo.inc. Some register overlaps are generated twice in this file, leading to a compilation error. I think this is because in RegisterInfoEmitter.cpp, RegisterAliases are declared as "std::map<Record*, std::set<Record*>, LessRecord>" and a requirement for std::map is that the comp...

Yes, the arch is just as you said, something like AMD GPU, but Intel GPU don't have separate register file for 'scalar/vector'. In fact my idea of defining the register tuples was borrowed from SIRegisterInfo.td in AMD GPU. But seems that AMD GPU mainly support i32/i64 register type, while Intel GPU also support byte/short register type. So I have to start defining the registers from 'byte' type, and then build up other type registers through RegisterTuples. I thought RegisterTuple is kind of ex...

...it doesn't just work problem I faced. > Moving the code to the disassembler generator makes sense, although at least on PowerPC, we have equivalent tables in the AsmParser and we should eliminate them in both places. Hum. Curious. I don't feel so bad about generating them then in the RegisterInfo area, as it is just RegisterInfo. > I recommend only generating (or including) the tables upon request. Done. I did this in a way so that a first time port creator can easily discover the data in the .inc file, and if they want it, it then is obvious how to get it. I did a quick look through...

Hello, I have defined 8 registers in registerinfo.td file in the following order: R_0, R_1, R_2, R_3, R_4, R_5, R_6, R_7 But the generated assembly code only uses 2 registers. How to enable it to use all 8? Also can i control the ordering like after R_0 can i use R_5 without changes in registerinfo.td? What changes are required here? either in s...

i have loop index I. I want to increment it by 1. How to do this in registerinfo.td. I m trying following but getting error. let SubRegIndices = [sub_32bit, sub_32bit_hi], CoveredBySubRegs = 1 in { foreach I = 0-255 in { m=add(I,1); def R_#J#_REG64b_#I : R_P<"R_"#J#"_R64b_"#I, !shl(I,2), [!cast<R_P>("R_"#J#"_REG32b_"#I),...

...bove to happen rather it should increment R instead of V in this case. It should do something as follows: 1st load to take place in R_0_V_0 2nd load to take place in R_1_V_0 3rd load to take place in R_2_V_0 Now, how to achieve this? Can i mention some condition in instructioninfo.td file? and in registerinfo.td file instead of 1 object Reg_A, there will be 2 objects Reg_A and Reg_B where Reg_B defines same registers but in different order. Reg_B; R_0_V_0, R_1_V_0, R_2_V_0, //here R changes R_0_V_1, R_1_V_1, R_2_V_1, R_0_V_2, R_1_V_2, R_2_V_2, R_0_V_3, R_1_V_3, R_2_V_3. So that in instructioninfo.td...

...VRBaseMap.end() && "Node emitted out of order - late"); I am not sure why this assertion is being triggered or what I changed that is causing it. This is asserting when SDValue is FrameIndexSDNode 1. I don't have any code that modified frameindices until my overloaded RegisterInfo function. I've attached the bc file. If I generate an unoptimized bc file then there is no issue, only when I turn optimizations on do I hit this problem. Thanks for any hints, Micah Villmow Systems Engineer Advanced Technology & Performance Advanced Micro Devices Inc. S1-60...

Hello, I'm developing a llvm backend. It seems that, if i16 is not a legal type (no register can hold i16 types in RegisterInfo.td and as a RegisterClass in SelLowering.cpp), i16 should be promoted to i32. Nonotheless, this simple program: int main(){ volatile short a; a= 3; return 0; } which is trasformed in this IR: define i32 @main() nounwind readnone { entry: %a = alloca i16, align 2 ;...

...ich at any given time one of several backends is in use, just as in TableGen. The backends specify one or more record types and definitions. TableML then reads a configuration file, evaluates the definitions, and passes the results to the backend for serialization. For instance, we might have a RegisterInfo backend that declares a definition of "RegisterNames : string list". Then we could have a TableML input file like this: def val RegisterInfo = [ "eax", "ebx", "ecx", "edx" ] Or we could have a more complex one that performs computation to produc...

...LLVM Backend. There are three place to use TableGen in basic steps of document "Writing an LLVM Compiler Backend": 2. Describe the register set of the target. Use "TableGen" to generate code for register definition, register aliases, and register classes from a target-specific RegisterInfo.td input file. 3. Describe the instruction set of the target. Use "TableGen" to generate code for target-specific instructions from target-specific versions of TargetInstrFormats.td andTargetInstrInfo.td. 4. Describe the selection and conversion of the LLVM IR from a Directed Acyclic Gr...

...t;Node emitted out of order - late"); > > I am not sure why this assertion is being triggered or what I changed that > is causing it. > > This is asserting when SDValue is FrameIndexSDNode 1. > > I don't have any code that modified frameindices until my overloaded > RegisterInfo function. > > I've attached the bc file. If I generate an unoptimized bc file then there > is no issue, only when I turn optimizations on do I hit this problem. > I got this too. It's related to debug information being in flux right now. I believe that Devang is working on a fix...