search for: simplevaluetyp

...ss: IsSSA, TracksLiveness ... %31:sfgpr32 = ADDrr killed %32:sgpr32, %27:sgpr32 ... Here should not select f32 sfgpr32 register, debugger point to TargetRegisterInfo:: getCommonSubClass(const TargetRegisterClass *A, const TargetRegisterClass *B, const MVT::SimpleValueType SVT = MVT::SimpleValueType::Any) This function has been called 10+ in LLVM, only one place give specific SVT parameter. Most of those places are hard to get the MVT::SimpleValueType infos and use the default value. That's why sfgpr32 comes out. LLVM defect? - Best Regards...

I searched the archives and found this from last month: I ran into the same problem and fixed it by forcing the MVT::SimpleValueType enum to be 64 bits so that all of the types in the union later in the class are the same size. I tested this on ppc64 and x86_64. Index: include/llvm/CodeGen/ValueTypes.h =================================================================== --- include/llvm/CodeGen/ValueTypes.h (revision 66504)...

Because each channel contains 24-bit, so.. what is the llvm::SimpleValueType I should use for each channel? the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, f32, f64, f80, none of them are fit one channel (24-bit). I think I can use i32 or f32 to represent each 24-bit channel, if the runtime result of some machine instructions exceeds 23-bit (1 bit is for...

...integer type. See getExtendedIntegerVT. It's almost guaranteed you will have to change a chunk of target independent codegen to support the use of an extended type though. Evan On Nov 20, 2008, at 4:46 AM, Wei wrote: > Because each channel contains 24-bit, so.. what is the > llvm::SimpleValueType I should use for each channel? > the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, f32, > f64, f80, none of them are fit one channel (24-bit). > > I think I can use i32 or f32 to represent each 24-bit channel, if the > runtime result of some machine instructions exce...

...uched, too. The value of the 'd' channel of Rt1 plus the 'd' channel of Rt2 (i.e. 'b' from R1 + 'a' from R2, because R1.aba'b' and R2.bba'a') will be lost, too. I don't know whether I can set the 'type' of such register using a llvm::MVT::SimpleValueType? According the LLVM doc & LLVM source codes, I think llvm::MVT::v8i8, v2f32, etc is used to represent register for SIMD instructions. I don't think the operations in my platform are SIMD instructions. However, I can not find any llvm::MVT::SimpleValueType which can represents a 96-bit regi...

...koji.fedoraproject.org/koji/taskinfo?taskID=1148023 > > make[1]: Entering directory `/builddir/build/BUILD/llvm-2.5/lib/VMCore' > llvm[1]: Building Intrinsics.gen.tmp from Intrinsics.td > tblgen: IntrinsicEmitter.cpp:137: void > EmitTypeForValueType(std::ostream&, llvm::MVT::SimpleValueType): > Assertion `false && "Unsupported ValueType!"' failed. > make[1]: Leaving directory `/builddir/build/BUILD/llvm-2.5/lib/VMCore' > make[1]: *** [/builddir/build/BUILD/llvm-2.5/lib/VMCore/Release/Intrinsics.gen.tmp] > Aborted > make: *** [all] Error 1 >...

...apparently has a #pragma which can be used to do it and gcc 4.3 seems to be happy with the hack described but as Duncan says trying to force this behavior in a union is probably less than desirable in the long term. Another ugly hack that I tried: union { uintptr_t V; #ifdef _LP64 SimpleValueType SimpleTyU[2]; # define SimpleTy SimpleTyU[1] #else SimpleValueType SimpleTyU[1]; # define SimpleTy SimpleTyU[0] #endif const Type *LLVMTy; }; This works on my big endian 64-bit system but I've not seen what damage it may do on other platform types. On 4/7/09 4:09 PM, "A...

...#39;d' > channel of Rt1 plus the 'd' channel of Rt2 (i.e. 'b' from R1 + 'a' > from R2, because R1.aba'b' and R2.bba'a') will be lost, too. > > I don't know whether I can set the 'type' of such register using a > llvm::MVT::SimpleValueType? > According the LLVM doc & LLVM source codes, I think llvm::MVT::v8i8, > v2f32, etc is used to represent register for SIMD instructions. > I don't think the operations in my platform are SIMD instructions. > However, I can not find any llvm::MVT::SimpleValueType which can...

...have 17 bits of mantissa - so it may be a tight squeeze without 24 bit integer ops (shifts and ands and stuff will also be a painful, but that's a more expansive topic). Dan On Nov 20, 2008, at 7:46 AM, Wei wrote: > Because each channel contains 24-bit, so.. what is the > llvm::SimpleValueType I should use for each channel? > the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, f32, > f64, f80, none of them are fit one channel (24-bit). > > I think I can use i32 or f32 to represent each 24-bit channel, if the > runtime result of some machine instructions exce...

...build on ppc64: http://koji.fedoraproject.org/koji/taskinfo?taskID=1148023 make[1]: Entering directory `/builddir/build/BUILD/llvm-2.5/lib/VMCore' llvm[1]: Building Intrinsics.gen.tmp from Intrinsics.td tblgen: IntrinsicEmitter.cpp:137: void EmitTypeForValueType(std::ostream&, llvm::MVT::SimpleValueType): Assertion `false && "Unsupported ValueType!"' failed. make[1]: Leaving directory `/builddir/build/BUILD/llvm-2.5/lib/VMCore' make[1]: *** [/builddir/build/BUILD/llvm-2.5/lib/VMCore/Release/Intrinsics.gen.tmp] Aborted make: *** [all] Error 1 The compiler flags used are...

...ypes. It's the use of HasOneImplicitDefWithKnownVT() that scares me, I don't think there is any workaround for that. /jakob /// HasOneImplicitDefWithKnownVT - If the instruction has at least one /// implicit def and it has a known VT, return the VT, otherwise return /// MVT::Other. MVT::SimpleValueType CodeGenInstruction:: HasOneImplicitDefWithKnownVT(const CodeGenTarget &TargetInfo) const { if (ImplicitDefs.empty()) return MVT::Other; // Check to see if the first implicit def has a resolvable type. Record *FirstImplicitDef = ImplicitDefs[0]; assert(FirstImplicitDef->isSubClassOf...

....td files that I¹ll be creating. So I used svn to grab the code from the repository and ran configure and make. However, the build breaks at this point: llvm[1]: Building Intrinsics.gen.tmp from Intrinsics.td tblgen: IntrinsicEmitter.cpp:163: void EmitTypeForValueType(std::ostream&, llvm::MVT::SimpleValueType): Assertion `false && "Unsupported ValueType!"' failed. 0 tblgen 0x00000000801be2bc 1 tblgen 0x00000000801bea14 2 tblgen 0x000003ffffad4b84 3 libc.so.6 0x0000020000286ef0 gsignal + 76 4 libc.so.6 0x0000020000288330 abort + 256 5 libc.so.6 0x000002000027ed...

...most guaranteed you   > will have to change a chunk of target independent codegen to support   > the use of an extended type though. > > Evan > > On Nov 20, 2008, at 4:46 AM, Wei wrote: > > > > > Because each channel contains 24-bit, so.. what is the > > llvm::SimpleValueType I should use for each channel? > > the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, f32, > > f64, f80, none of them are fit one channel (24-bit). > > > I think I can use i32 or f32 to represent each 24-bit channel, if the > > runtime result of some machi...

Hi, > llvm[1]: Building Intrinsics.gen.tmp from Intrinsics.td > tblgen: IntrinsicEmitter.cpp:163: void EmitTypeForValueType(std::ostream&, > llvm::MVT::SimpleValueType): Assertion `false && "Unsupported ValueType!"' > failed. this came up before IIRC, but I don't remember the details - buggy system compiler? Try searching the archives. Also, if you were compiling with optimization, try building without optimization. Ciao, Duncan...

Hi, I'm trying to do a Debug build for the 1st time and I keep getting this assertion: llvm-tblgen: CodeGenDAGPatterns.cpp:64: llvm::EEVT::TypeSet::TypeSet(llvm::ArrayRef<llvm::MVT::SimpleValueType>): Assertion `!VTList.empty() && "empty list?"' failed. I do not know what list this assertion is referring to. Does anyone know? I always did Release builds before without any problem. Thanks. -------------- next part -------------- An HTML attachment was scrubbed... UR...

Hi all. I'm looking for a ways of defining register files with non-standard machine value type in tablegen. The value types not covered by SimpleValueType enum. For example (from the top of my head) 25 bit integers, or 8 way 18 bit integers. These types going to be used with intrinsics so I also need appropriate C custom types defined. I wonder if I can describe those in tablegen files or do I need to extend llvm. What is the right way of supportin...

...2, v32f64 although i have defined them appropriately in all the files like machinevaluetype.h, valuetypes.cpp etc. i have checked it many times but still getting the following error when build in debug mode. llvm-tblgen: /utils/TableGen/CodeGenDAGPatterns.cpp:57: llvm::EEVT::TypeSet::TypeSet(MVT::SimpleValueType, llvm::TreePattern &): Assertion `(VT < MVT::LAST_VALUETYPE || VT == MVT::iPTR || VT == MVT::iPTRAny || VT == MVT::Any) && "Not a concrete type!"' failed. What could be the reason?? please guide how to define new types in llvm backend. Thank You -------------- next...

...Node(ISD::BITCAST, dl, VT, Op); } The input Op is <4 x i8> = and <4 x i8>, <4 x i8>. The result of TLI.getTypeToPromoteTo(ISD::AND, MVT::v4i8) is MVT::v2i32; The reason why this occurs is: // See if this has an explicit type specified. std::map<std::pair<unsigned, MVT::SimpleValueType>, MVT::SimpleValueType>::const_iterator PTTI = PromoteToType.find(std::make_pair(Op, VT.getSimpleVT().SimpleTy)); if (PTTI != PromoteToType.end()) return PTTI->second; assert((VT.isInteger() || VT.isFloatingPoint()) && "Cannot autopromot...

...squeeze without 24 bit integer ops   > (shifts and ands and stuff will also be a painful, but that's a more   > expansive topic). > > Dan > > On Nov 20, 2008, at 7:46 AM, Wei wrote: > > > > > Because each channel contains 24-bit, so.. what is the > > llvm::SimpleValueType I should use for each channel? > > the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, f32, > > f64, f80, none of them are fit one channel (24-bit). > > > I think I can use i32 or f32 to represent each 24-bit channel, if the > > runtime result of some machi...

...to change a chunk of target independent codegen to support >> the use of an extended type though. >> >> Evan >> >> On Nov 20, 2008, at 4:46 AM, Wei wrote: >> >> >> >>> Because each channel contains 24-bit, so.. what is the >>> llvm::SimpleValueType I should use for each channel? >>> the current llvm::SimpleValueType contains i1, i8, i16, i32, i64, >>> f32, >>> f64, f80, none of them are fit one channel (24-bit). >> >>> I think I can use i32 or f32 to represent each 24-bit channel, if >>>...