Displaying 6 results from an estimated 6 matches for "simplev".
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2015 Sep 13
3
RFC: faster simplifyInstructionsInBlock/SimplifyInstructions pass
...emove the instruction.
I->eraseFromParent();
// Only add the operands to the worklist if their uses are now empty,
// to avoid needlessly revisiting instructions.
for (auto U : Operands)
if (U->use_empty())
WorkList.insert(U);
return true;
}
if (Value *SimpleV = SimplifyInstruction(I, DL)) {
// Add the users to the worklist.
for (User *U : I->users())
WorkList.insert(cast<Instruction>(U));
// Replace the instruction with its simplified value.
I->replaceAllUsesWith(SimpleV);
// Gracefully handle edge cases where the...
2013 Oct 25
1
replace a value in file
Hi
I would lie replace a value in my config file
/etc/default/fusioninventory-agent
MODE = daemon
and i would like replace cron by daemon
My manifest is this but is not good, can you have an idea? I think it s
Simplevers.lns is not good..
augeas { ''fusioninventory mode'':
lens => ''Simplevars.lns'',
incl => ''/etc/default/fusioninventory-agent'',
changes => [ ''set MODE daemon'' ],...
2019 Sep 30
2
Adding support for vscale
I've posted two patches on Phabricator to add support for VScale in LLVM.
A brief recap on `vscale`:
The scalable vector type in LLVM IR is defined as `<vscale x n x m>`, to create types such as `<vscale x 16 x i8>` for a scalable vector with at least 16 bytes. In the definition of the scalable type, `vscale` is specified as a positive constant of type integer that will only be
2019 Mar 18
6
Scalable Vector Types in IR - Next Steps?
On Fri, Mar 15, 2019 at 1:55 PM Chandler Carruth via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
>
> On Fri, Mar 15, 2019 at 11:22 AM Finkel, Hal J. via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>>
>> On 3/15/19 10:58 AM, David Greene wrote:
>> > Renato Golin <rengolin at gmail.com> writes:
>> >
>> >> On Fri, 15 Mar 2019 at
2019 Sep 30
3
Adding support for vscale
...e the actual full vector size, not related to VL.
Regardless, setting it even as *runtime* constant seems to be a red flag.
What is vscale intended for, and how does it relate to Cray-like Vector
Length?
> Additionally, we (libre-riscv) are working on a similar scalar vectors
> ISA called SimpleV that also allows changing VL at runtime and we are
> planning on basing it on LLVM's scalable vector support.
Both SV and RVV are based on Cray VL which is a runtime global CSR setting
the number of elements to be processed in any given vector loop.
The difference is that RVV *requests* a...
2018 Aug 06
2
vectorisation, risc-v
...not had it confirmed.
As an aside I have to say that I am extremely surprised to learn that it is
only in the past year that vectorisation or more specifically variable
length SIMD has hit mainstream in libre licensed toolchains, through ARM
and RISCV.
So some background : I am the author of the SimpleV extension, which has
been developed to provide a uniform *parallelism* API, *not* as a new
Vector Microarchitecture (a common misconception). It has unintended
sideeffects such as providing LD/ST multi with predication, which in turn
can be used on function entry or context switch to save or load *...