Displaying 11 results from an estimated 11 matches for "simm13".
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simm16
2007 Dec 03
2
[LLVMdev] Using frameindex in a pattern
...ADDRri will eventually turn into register+constant
addressing in assembler.
The IA64 target has explicit case in it's Select method
to handle frameindex -- which is fine, but I though I'd
try a fully declarative method, so I've added to sparc
the following:
def : Pat<(frameindex simm13:$val), (add G0, simm13:$val)>;
(Ignore bogus G0, and '13' -- just for testing). The error
I get this:
/home/ghost/Build/llvm/Release/bin/tblgen:
In anonymous.24: frameindex node requires exactly 0 operands!
Is this really as designed, or nobody got around to making frameindex
h...
2007 Dec 04
0
[LLVMdev] Using frameindex in a pattern
...ster+constant
> addressing in assembler.
>
> The IA64 target has explicit case in it's Select method
> to handle frameindex -- which is fine, but I though I'd
> try a fully declarative method, so I've added to sparc
> the following:
>
> def : Pat<(frameindex simm13:$val), (add G0, simm13:$val)>;
>
> (Ignore bogus G0, and '13' -- just for testing). The error
> I get this:
>
> /home/ghost/Build/llvm/Release/bin/tblgen:
> In anonymous.24: frameindex node requires exactly 0 operands!
>
>
> Is this really as designed, or n...
2007 Dec 04
1
[LLVMdev] Using frameindex in a pattern
...g in assembler.
>>
>> The IA64 target has explicit case in it's Select method
>> to handle frameindex -- which is fine, but I though I'd
>> try a fully declarative method, so I've added to sparc
>> the following:
>>
>> def : Pat<(frameindex simm13:$val), (add G0, simm13:$val)>;
>>
>> (Ignore bogus G0, and '13' -- just for testing). The error
>> I get this:
>>
>> /home/ghost/Build/llvm/Release/bin/tblgen:
>> In anonymous.24: frameindex node requires exactly 0 operands!
>>
>>
>&...
2011 Nov 08
0
[LLVMdev] Newbie Question: How are the values set in a Sparc store instruction (e.g. STri)?
...[(store IntRegs:$src, ADDRri:$addr)]>;
F3_2 and it's superclasses are defined as follows:
class F3_2<bits<2> opVal, bits<6> op3val, dag outs, dag ins,
string asmstr, list<dag> pattern> : F3<outs, ins, asmstr,
pattern> {
bits<13> simm13;
let op = opVal;
let op3 = op3val;
let Inst{13} = 1; // i field = 1
let Inst{12-0} = simm13;
}
class F3<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSP<outs, ins, asmstr, pattern> {
bits<5> rd;
bits<6> op3;
bits&l...
2013 Mar 24
5
[LLVMdev] Types in TableGen instruction selection patterns
...n emits lots of type inference errors when multiple types are added to a register class.
In the output pattern, it is no longer necessary to duplicate the register classes or types of register operands.
For immediate operands, the 'imm' tag is still required:
def : Pat<(subc i32:$b, simm13:$val), (SUBCCri $b, imm:$val)>;
I would like for the old register class notation to go away eventually.
/jakob
2013 Apr 20
0
[LLVMdev] Types in TableGen instruction selection patterns
...errors when multiple types are added to a register class.
>
> In the output pattern, it is no longer necessary to duplicate the register classes or types of register operands.
>
> For immediate operands, the 'imm' tag is still required:
>
> def : Pat<(subc i32:$b, simm13:$val), (SUBCCri $b, imm:$val)>;
>
>
> I would like for the old register class notation to go away eventually.
>
Hi Jakob,
I'm going through the R600 target and converting all the patterns to the
new syntax, and I've come across a pattern that I'm unable to convert:...
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
...uot;),
[(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
def ri : F3_2<2, Op3Val,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
!strconcat(OpcStr, " $b, $c, $dst"),
[(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
}
which allows it to use instructions like:
defm AND : F3_12<"and" , 0b000001, and>;
defm OR : F3_12<"or" , 0b000010, or>;
defm XOR : F3_12<"xor" , 0b000011, xor>;
defm SLL : F3_12<"sll" , 0b100101, shl>;...
2007 Oct 19
0
[LLVMdev] Adding address registers to back-end
...[(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:
$c))]>;
def ri : F3_2<2, Op3Val,
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
!strconcat(OpcStr, " $b, $c, $dst"),
[(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
}
defm ADD : F3_12<"add", 0b000000, add>;
Instruction ADD output register class is IntRegs. It does not match
AddrRegs. That's why you are getting the assertion.
What you need is to define a parallel set of instructions that target
the address register class....
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2007 Oct 19
2
[LLVMdev] Adding address registers to back-end
Hi!
I'm writing a new back-end for a new architecture. First, I'll do
some "tests" with an existing back-end (I chose the Sparc back-end).
My architecture has special address-registers and I want to add such
new address-registers to my Sparc back-end.
1) I defined a new register call AddrRegs
2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. ))
3) I
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
...[(set IntRegs:$dst, (OpNode IntRegs:$b,
IntRegs:$c))]>;
> def ri : F3_2<2, Op3Val,
> (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
> !strconcat(OpcStr, " $b, $c, $dst"),
> [(set IntRegs:$dst, (OpNode IntRegs:$b,
simm13:$c))]>;
> }
>
> which allows it to use instructions like:
>
> defm AND : F3_12<"and" , 0b000001, and>;
> defm OR : F3_12<"or" , 0b000010, or>;
> defm XOR : F3_12<"xor" , 0b000011, xor>;
> defm SLL : F3_12&...