search for: simm12

I'm trying to write a tablegen pattern to that matches a sequence of SDNodes and emits again an SDNode and another instruction. The pattern I've written looks like the folowing: def : Pat<(foo (bar GPR:$rs1), simm12:$imm1), (bar (BAZ GPR:$rs1, simm12:$imm1))>; foo and bar are SDNodes, BAZ is an instruction. In particular, bar is defined as follows: def bar : SDNode<"ISD::BAR", SDTIntUnaryOp>; The basic idea of this pattern is to propagate bar over certain instructions until they...

Hi Im trying to add RISC V Store Instruction for an Experiment on my Target. The thing is, llvm Store Format gets Register and Pointer Type Operand. beside this, RISC-V Store Instruction takes source Register, Base Register and offset immediate type. So this takes 3 leafs. In this case, should I make new SelectionDAG Node in this case? or use BuildMI Instruction to add new Register? P.S.