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Preallocation Instruction Scheduling with Register Pressure Minimization Using a Combinatorial Optimization Approach G. Shobaki, M. Shawabkeh and N. Abu-Rmaileh ACM Transactions on Architecture and Code Optimization (TACO). vol. 10, issue 3, Article 14 (Sept. 2013) http://dx.doi.org/10.1145/2512432 Regards Ghassan Shobaki, PH.D Assistant Professor Department of Computer Science Princess Sumaya University for Technology...

Thank you for the answers, Jakob! That's really informative for someone who is still new to LLVM like me. Please see my responses below. -Ghassan  ________________________________ From: Jakob Stoklund Olesen <stoklund at 2pi.dk> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Tuesday, August 16, 2011 12:52 AM Subject: Re: [LLVMdev] Register Pressure Computation during Pre-Allocation Scheduling On Aug 15, 2011, at 1:27 AM, Ghassan Shobaki wrote: >This...

...s message mean? Is this a bug or we are doing something wrong? How can we test the MI scheduler by itself? Is it interesting to test 3.3 or there are interesting features that were added to the trunk after branching 3.3? In the latter case, we are willing to test the trunk. Thanks Ghassan Shobaki Assistant Professor Department of Computer Science Princess Sumaya University for Technology Amman, Jordan ________________________________ From: Andrew Trick <atrick at apple.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" <...

...tics and at least capture loop nesting levels. With such static info, we don't expect see blocks with zero frequency; we expect a block outside all loops to have a frequency of 1 or some small non-zero number. Does LLVM compute such static info? If yes, how do we enable that? Thanks Ghassan Shobaki Assistant Professor of Computer Science California State University, Sacramento ________________________________ From: qcolombet at apple.com <qcolombet at apple.com> on behalf of Quentin Colombet <qcolombet at apple.com> Sent: Wednesday, September 20, 2017 9:44:35 AM To: Kerbow, Aus...

...on this, but are there any known facts that explain this behavior? Is this caused by a known regression in scheduling and/or allocation (which I doubt) or by the implementation (or enabling) of some new optimization(s) that naturally increase(s) register pressure? Thank you in advance! Ghassan Shobaki Assistant Professor Department of Computer Science Princess Sumaya University for Technology Amman, Jordan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130628/aa8126ee/attachment.html>

Sent from my iPhone On Jun 28, 2013, at 2:38 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi, > > We are currently in the process of upgrading from LLVM 2.9 to LLVM 3.3. We are working on instruction scheduling (mainly for register pressure reduction). I have been following the llvmdev mailing list and have learned that a machine...

...ll consume less overall energy. There is some academic research on this with simulation data, but I am not aware of any actual implementation in a production compiler that proves actual energy reduction. Has anyone ever implemented and experimented with such optimizations in LLVM? Thanks Ghassan Shobaki, PH.D Assistant Professor Department of Computer Science Princess Sumaya University for Technology Amman, Jordan ________________________________ From: Sean Silva <silvas at purdue.edu> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" &...

So, when the MI scheduler is enabled, will SD scheduling be totally disabled or the SD scheduler will be automatically set to do source scheduling? -Ghassan ________________________________ From: Andrew Trick <atrick at apple.com> To: llvmdev at cs.uiuc.edu Cc: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Sent: Thursday, September 26, 2013 9:24 AM Subject: Re: [LLVMdev] Enabling MI Scheduler on x86 (was Experimental Evaluation of the Schedulers in LLVM 3.3) On Sep 23, 2013, at 11:36 PM, Chandler Carruth <chandlerc at google.com> wrote: > >On...

I'm trying to compute and print a weighted spill cost based upon the execution frequency of the basic block where the spill is inserted. My goal is to analyse what effect scheduling changes have on the sum of this weighted spill cost in some benchmarks. I've experimented doing this directly before a spill is inserted in InlineSpiller.cpp using MBFI.getBlockFreq()

...on into account? We are currently working on a research project on instruction scheduling for low power (experimenting with different algorithms for minimizing switching power) and would like to find out if anyone in the LLVM community is interested in adding this feature to LLVM. Regards Ghassan Shobaki, PH.D Assistant Professor Department of Computer Science Princess Sumaya University for Technology Amman, Jordan -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20130414/bf1ca8a0/attachment.html>

On Jul 2, 2013, at 2:35 PM, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Thank you for the answers! We are currently trying to test the MI scheduler. We are using LLVM 3.3 with Dragon Egg 3.3 on an x86-64 machine. So far, we have run one SPEC CPU2006 test with the MI scheduler enabled using the option -fplugin-arg-dragon...

Hi Andy, Please see my in-line answers below. Regards -Ghassan ________________________________ From: Andrew Trick <atrick at apple.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Friday, September 23, 2011 8:02 PM Subject: Re: [LLVMdev] Pre-Allocation Schedulers in LLVM On Sep 23, 2011, at 6:16 AM, Ghassan Shobaki wrote: Hi Andrew, > > >What we have...

...-unit information. However, we are interested in adding both, but we would like to do it in two steps (first latency only then functional unit info) and measure the impact of each step. Regards -Ghassan ________________________________ From: Andrew Trick <atrick at apple.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Wednesday, September 21, 2011 6:54 AM Subject: Re: [LLVMdev] Pre-Allocation Schedulers in LLVM On Sep 17, 2011, at 10:07 AM, Ghassan Shobaki wrote: Hi, > > >I am currently wri...

On Aug 15, 2011, at 1:27 AM, Ghassan Shobaki wrote: > One factor that is causing our current register pressure estimate to be off is not being able to properly account for live-in and live-out registers (both virtual and physical). As far as we can tell, LLVM represents live-in regs with CopyFromReg instrs and live-out regs with CopyToReg...

On Sep 23, 2011, at 6:16 AM, Ghassan Shobaki wrote: > Hi Andrew, > > What we have is not a patch to any of LLVM's schedulers. We have implemented our own scheduler and integrated it into LLVM 2.9 as yet-another scheduler. Our scheduler uses a combinatorial optimization approach to balance ILP and register pressure. In one exper...

I have been doing some benchmarking on x86 using llvm 2.9 with the llvm-gcc 4.2 front end. I noticed that the -march and -mtune options make a significant positive difference in x86-32 mode but hardly make any difference in x86-64 mode. The small difference that I am measuring when the target is x86-64 could easily be random variation, while for the x86-32 target I am measuring a huge difference

...suite with comparable size, he may get different execution-time results, but most likely he will get the same spill count results that we got (of course, I mean the relative results). -Ghassan  ________________________________ From: Renato Golin <renato.golin at linaro.org> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: Andrew Trick <atrick at apple.com>; "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Thursday, September 19, 2013 8:27 PM Subject: Re: [LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3 On 19 September 2013 17:...

...rticularly surprising for you? The low impact of the MI scheduler, the relatively good performance of the source scheduler or the relatively poor performance of the ILP scheduler? Thanks -Ghassan  ________________________________ From: Benjamin Kramer <benny.kra at gmail.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: Andrew Trick <atrick at apple.com>; "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Thursday, September 19, 2013 4:53 PM Subject: Re: [LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3 On 17.09.2013, at 20:04,...

On 26 September 2013 08:30, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > So, when the MI scheduler is enabled, will SD scheduling be totally disabled > or the SD scheduler will be automatically set to do source scheduling? The latter. The SD scheduler is where the DAG is converted into the linear MachineInstr represen...

Hi Renato, Please see my answers below. Thanks -Ghassan ________________________________ From: Renato Golin <renato.golin at linaro.org> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: Andrew Trick <atrick at apple.com>; "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Thursday, September 19, 2013 5:30 PM Subject: Re: [LLVMdev] Experimental Evaluation of the Schedulers in LLVM 3.3 On 17 September 2013 19:...