search for: shifts

I am getting the following message when Shorewall stops can anybody shed any light on this message and where I should be looking? Thanks root@bobshost:~# shorewall stop Loading /usr/share/shorewall/functions... Processing /etc/shorewall/params ... Processing /etc/shorewall/shorewall.conf... Loading Modules... Stopping Shorewall...Processing /etc/shorewall/stop ... IP Forwarding Enabled

Hi all, I'm running a monte carlo test of a neural network tool I've developed, and it looks like it's going to take a very long time if I run it in R so I'm interested in translating my code (included below) into something faster like Fortran (which I'll have to learn from scratch). However, as you'll see my code loads the nnet library and uses it quite a bit, and I

...let me see again.. > 2) Are we possibly missing opportunities by not exploiting knowledge of > the a known negative shift amount? Anything specific you are thinking of? > > But the transform is limited to single-use sext. > > We can quite trivially get a case where there are two shifts by the same sext: > > https://godbolt.org/z/j6mO3t <- We should handle those cases. > > > > In https://reviews.llvm.org/D68103#1686130 Sanjay Patel notes that this > > sext is intrusive for analysis, that we will gain far better analysis with zext, > > so we should...

...no need to introduce any special poison blocking behavior). On Mon, Feb 25, 2019 at 4:01 PM Nuno Lopes <nunoplopes at sapo.pt> wrote: > You are very right! Transformation to rotate is correct. > > So I guess the remaining case is if you want to be able to transform > funnel > shifts into other arithmetic operations when %x != %y. I think I saw some > optimizations where fshl was being transformed into shl. This wouldn't be > OK > because shl doesn't stop poison. Unless these are only being done for > guaranteed non-zero %sh? Then it's ok because fshl ca...

The thing is, we *don't* "not demand" those high bits. We *don't* not care what's in those bits - IR shifts don't mask their shift amounts. I.e we can't replace `x >> (32-y)` with `x >> (-y)`, which would be legal transform should we not demand those bits. We very much demand them. We just know those bits to be zero. And i'm not sure how to convey that to SimplifyDemandedBits()....

Hi, > I'm working in adding support for 64-bit integers to my target. I'm using > LLVM to decompose the 64-bit integer operations by using 32-bit registers > wherever possible and emulating support where not. When looking at the bit > shift decomposition I saw what seems to be a bug in the implementation. The > affected function is ExpandShiftWithUnknownAmountBit in >

In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext is simply a shift-by-zext. But the transform is limited to single-use sext. We can quite trivially get a case where there are two shifts by the same sext: https://godbolt.org/z/j6mO3t <- We should handle those cases. In https://reviews.llvm.org/D68103#1686130 Sanjay Patel notes that this sext is intrusive for analysis, that we will gain far better analysis with zext, so we should just ignore forego of the one-use check, and sim...

Hi Duncan, The problem is the implementation of the expansion. Perhaps an example can help illustrate better. Take the case of a 64-bit integer shifted left by say 6 bits and is decomposed using 32-bit registers. Because 6 is less than the 32 (the register size) the resulting low part should be equal to the source low part shifted left by 6 bits. The current implementation places a zero

...touch the poison when sh==0 %rotate = fshl %x, %x, %sh ; if x is poison, the op is unquestionably producing poison; there's no sh==0 loophole here On Mon, Feb 25, 2019 at 1:12 PM Nuno Lopes <nunoplopes at sapo.pt> wrote: > Thanks Sanjay! > > I did a quick study of these funnel shifts: > The generic lowering to SDAG is correct for the optimization below. It > actually stops poison if shift amount is zero: > SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC); > (...) > SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ); >...

Hi all, I was trying to test ROUTE specific code with a multi-isp serviced box. There is a bug somewhere, but I''m not able to understand what the real problem is: when I issue a "shorewall show capabilities" I get: Loading /usr/share/shorewall/functions... Processing /etc/shorewall/params ... Processing /etc/shorewall/shorewall.conf... Loading Modules... Shorewall has

...3 PM John Regehr via llvm-dev < llvm-dev at lists.llvm.org> wrote: > Great to see you've avoided the less-than-obvious pitfall of > transforming funnel shift by not-constant into a shift! > > (Background for people not following this as closely: Unlike LLVM's > regular shifts, the funnel shifts mask the shift exponent. This removes > potential UBs but also introduces an impedance mismatch WRT shift.) > > John > > > On 2/25/19 4:17 PM, Sanjay Patel wrote: > > We have these transforms from funnel shift to a simpler shift op: > > // fsh...

...d love to be proven wrong though!) > > Roman. > > On Tue, Oct 1, 2019 at 11:17 PM Roman Lebedev <lebedev.ri at gmail.com> wrote: > > > > The thing is, we *don't* "not demand" those high bits. > > We *don't* not care what's in those bits - IR shifts don't mask their > > shift amounts. > > I.e we can't replace `x >> (32-y)` with `x >> (-y)`, > > which would be legal transform should we not demand those bits. > > We very much demand them. We just know those bits to be zero. > > > > And i...

...> So I have this so far: > > declare i32 @llvm.catshift.i32(i32 %a, i32 %b, i32 %shift_amount) > declare <2 x i32> @llvm.catshift.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %shift_amount) > > For scalars, @llvm.catshift concatenates %a and %b, shifts the > concatenated value right by the number of bits specified by > %shift_amount modulo the bit-width, and truncates to the original > bit-width. > For vectors, that operation occurs for each element of the vector: >    result[i] = trunc(concat(a[i], b[i]) >> c[i]) > If...

There's a question about the behavior of funnel shift [1] + select and poison here that reminds me of previous discussions about select and poison [2]: https://github.com/AliveToolkit/alive2/pull/32#discussion_r257528880 Example: define i8 @fshl_zero_shift_guard(i8 %x, i8 %y, i8 %sh) { %c = icmp eq i8 %sh, 0 %f = fshl i8 %x, i8 %y, i8 %sh %s = select i1 %c, i8 %x, i8 %f ; shift amount is 0

Hi, is there any function in R that shifts elements of a vector to the opposite direction of what Lag() of the Hmisc package does? (something like, Lag(x, shift = -1) ) Thanks Zava -------------------------------------------------------- This is not an offer (or solicitation of an offer) to buy/se...{{dropped}}

Yes, this is such a case. However, implementing this in a future encoder/decoder would break compatibility with most (likely all) existing decoders, and only in some very, very rare cases where the material is such that the encoder chooses to use negative shifts, which makes it even harder to troubleshoot. Furthermore, as this can only be used in very rare cases, there is no benefit from allowing this. Op vr 19 jun. 2020 om 18:03 schreef Stephen F. Booth <me at sbooth.org>: > Is this a case where something allowed by the specification isn't...

In 780427f0e11 (Indicate that clock was set in the pvclock gtod notifier), logic was added to pass a CLOCK_WAS_SET notification to the pvclock notifier chain. While that patch added a action flag returned from accumulate_nsecs_to_secs(), it only uses the returned value in one location, and not in the logarithmic accumulation. This means if a leap second triggered during the logarithmic

System config:- bash-3.2# ifconfig -a lo0: flags=2001000849<UP,LOOPBACK,RUNNING,MULTICAST,IPv4,VIRTUAL> mtu 8232 index 1 inet 127.0.0.1 netmask ff000000 rge0: flags=201004843<UP,BROADCAST,RUNNING,MULTICAST,DHCP,IPv4,CoS> mtu 1500 index 2 inet 192.168.1.53 netmask ffffff00 broadcast 192.168.1.255 ether 0:1e:8c:25:cc:a5 lo0:

...These are useful for implementing the Embedded-C fixed-point arithmetic support in Clang, as previously detailed and discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-August/125433.html http://lists.llvm.org/pipermail/cfe-dev/2018-May/058019.html It is of course possible to emit these shifts as regular IR instructions, but targets which support saturating shifts might have difficulties efficiently selecting native instructions if the optimizer undoes the particular expected instruction pattern that the shifts would be selected on. / Bevin -------------- next part -------------- An HTM...

basically I need to create a sliding window in a string. a way to explain this is: > v <-