search for: shift

I am getting the following message when Shorewall stops can anybody shed any light on this message and where I should be looking? Thanks root@bobshost:~# shorewall stop Loading /usr/share/shorewall/functions... Processing /etc/shorewall/params ... Processing /etc/shorewall/shorewall.conf... Loading Modules... Stopping Shorewall...Processing /etc/shorewall/stop ... IP Forwarding Enabled

...Rouder et al (2005), #which attempts to test the estimation of weibull distribution parameters #from sample data. In this implementation, their HB estimation method is #replaced by an iterative neural network approach. library(nnet) data.gen=function(iterations,min.sample.size,max.sample.size,min.shift,max.shift,min.scale,max.scale,min.shape,max.shape){ #set up some collection vectors sample.size=vector(mode="numeric",length=iterations) exp.shift=vector(mode="numeric",length=iterations) exp.scale=vector(mode="numeric",length=iterations) exp.shape=...

Thanks for taking a look! On Tue, Oct 1, 2019 at 9:09 PM Philip Reames <listmail at philipreames.com> wrote: > On 9/27/19 1:40 PM, Roman Lebedev via llvm-dev wrote: > > In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext > > is simply a shift-by-zext. > > Just to make sure I'm following, the reasoning here is that the shift > amount must be positive or the shift would produce poison? And thus, > it's safe to assume that the sext == zext because we've (at worst) > removed UB...

We have these transforms from funnel shift to a simpler shift op: // fshl(X, 0, C) -> shl X, C // fshl(X, undef, C) -> shl X, C // fshl(0, X, C) -> lshr X, (BW-C) // fshl(undef, X, C) -> lshr X, (BW-C) These were part of: https://reviews.llvm.org/D54778 In all cases, one operand must be 0 or undef and t...

The thing is, we *don't* "not demand" those high bits. We *don't* not care what's in those bits - IR shifts don't mask their shift amounts. I.e we can't replace `x >> (32-y)` with `x >> (-y)`, which would be legal transform should we not demand those bits. We very much demand them. We just know those bits to be zero. And i'm not sure how to convey that to SimplifyDemandedBits()....

Hi, > I'm working in adding support for 64-bit integers to my target. I'm using > LLVM to decompose the 64-bit integer operations by using 32-bit registers > wherever possible and emulating support where not. When looking at the bit > shift decomposition I saw what seems to be a bug in the implementation. The > affected function is ExpandShiftWithUnknownAmountBit in > LegalizeIntegerTypes.cpp. Below is the original code and the proposed fix. > Could someone please review the changes? If they are correct how do I go > about...

In https://reviews.llvm.org/D68103 the InstCombine learned that shift-by-sext is simply a shift-by-zext. But the transform is limited to single-use sext. We can quite trivially get a case where there are two shifts by the same sext: https://godbolt.org/z/j6mO3t <- We should handle those cases. In https://reviews.llvm.org/D68103#1686130 Sanjay Patel notes that th...

Hi Duncan, The problem is the implementation of the expansion. Perhaps an example can help illustrate better. Take the case of a 64-bit integer shifted left by say 6 bits and is decomposed using 32-bit registers. Because 6 is less than the 32 (the register size) the resulting low part should be equal to the source low part shifted left by 6 bits. The current implementation places a zero instead. All other values have similar errors. Below i...

Don't we need to distinguish funnel shift from the more specific rotate? I'm not seeing how rotate (a single input op shifted by some amount) gets into trouble like funnel shift (two variables concatenated and shifted by some amount). Eg, if in pseudo IR we have: %funnel_shift = fshl %x, %y, %sh ; this is problematic because either x o...

...ora-rc3 2.6.11 kernel with ipset, ROUTE and policy patches applied. If someone has any hints on how to avoid this behaviour, I''ll be very gratefull. ________________________ Eduardo Ferreira Icatu Holding S.A. Supervisor de TI (5521) 3804-8606 -------------- next part -------------- + shift + nolock= + ''['' 1 -gt 1 '']'' + trap ''my_mutex_off; exit 2'' 1 2 3 4 5 6 9 + COMMAND=restart + case "$COMMAND" in + ''['' 1 -ne 1 '']'' + do_initialize + export LC_ALL=C + LC_ALL=C + umask 177 + PATH=/sbin:...

If I got poison propagation right, it's probably only by luck! Hopefully, the funnel shift bug is fixed here: https://reviews.llvm.org/rL354905 Nuno, IIUC this means that you do *not* need to change the funnel shift semantics in Alive. So I think that means we're still on track to go with John's suggestion that only select and phi can block poison? (I don't know of any obje...

...d love to be proven wrong though!) > > Roman. > > On Tue, Oct 1, 2019 at 11:17 PM Roman Lebedev <lebedev.ri at gmail.com> wrote: > > > > The thing is, we *don't* "not demand" those high bits. > > We *don't* not care what's in those bits - IR shifts don't mask their > > shift amounts. > > I.e we can't replace `x >> (32-y)` with `x >> (-y)`, > > which would be legal transform should we not demand those bits. > > We very much demand them. We just know those bits to be zero. > > > > And i...

On 7/2/2018 3:16 PM, Sanjay Patel wrote: > I also agree that the per-element rotate for vectors is what we want for > this intrinsic. > > So I have this so far: > > declare i32 @llvm.catshift.i32(i32 %a, i32 %b, i32 %shift_amount) > declare <2 x i32> @llvm.catshift.v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %shift_amount) > > For scalars, @llvm.catshift concatenates %a and %b, shifts the > concatenated value right by the number of bits speci...

There's a question about the behavior of funnel shift [1] + select and poison here that reminds me of previous discussions about select and poison [2]: https://github.com/AliveToolkit/alive2/pull/32#discussion_r257528880 Example: define i8 @fshl_zero_shift_guard(i8 %x, i8 %y, i8 %sh) { %c = icmp eq i8 %sh, 0 %f = fshl i8 %x, i8 %y, i8 %sh %s = select...

Hi, is there any function in R that shifts elements of a vector to the opposite direction of what Lag() of the Hmisc package does? (something like, Lag(x, shift = -1) ) Thanks Zava -------------------------------------------------------- This is not an offer (or solicitation of an offer) to buy/se...{{dropped}}

Yes, this is such a case. However, implementing this in a future encoder/decoder would break compatibility with most (likely all) existing decoders, and only in some very, very rare cases where the material is such that the encoder chooses to use negative shifts, which makes it even harder to troubleshoot. Furthermore, as this can only be used in very rare cases, there is no benefit from allowing this. Op vr 19 jun. 2020 om 18:03 schreef Stephen F. Booth <me at sbooth.org>: > Is this a case where something allowed by the specification isn't...

...100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -1297,7 +1297,7 @@ static inline unsigned int accumulate_nsecs_to_secs(struct timekeeper *tk) * Returns the unconsumed cycles. */ static cycle_t logarithmic_accumulation(struct timekeeper *tk, cycle_t offset, - u32 shift) + u32 shift, int *action) { cycle_t interval = tk->cycle_interval << shift; u64 raw_nsecs; @@ -1311,7 +1311,7 @@ static cycle_t logarithmic_accumulation(struct timekeeper *tk, cycle_t offset, tk->cycle_last += interval; tk->xtime_nsec += tk->xtime_interval <&lt...

System config:- bash-3.2# ifconfig -a lo0: flags=2001000849<UP,LOOPBACK,RUNNING,MULTICAST,IPv4,VIRTUAL> mtu 8232 index 1 inet 127.0.0.1 netmask ff000000 rge0: flags=201004843<UP,BROADCAST,RUNNING,MULTICAST,DHCP,IPv4,CoS> mtu 1500 index 2 inet 192.168.1.53 netmask ffffff00 broadcast 192.168.1.255 ether 0:1e:8c:25:cc:a5 lo0:

Hello, This is an RFC for adding intrinsics which perform saturating signed/unsigned left shift. There is currently a patch on Phabricator here: https://reviews.llvm.org/D83216 The intrinsics are of the form i32 @llvm.sshl.sat.i32(i32, i32) i32 @llvm.ushl.sat.i32(i32, i32) <4 x i32> @llvm.sshl.sat.v4i32(<4 x i32>, <4 x i32>) <4 x i32> @llvm.ushl.sat.v...

...f","g","h","i","j","k","l","m","n","o","p","q","r","s","t","u","v","w","x","y") > window <- 5 > shift <- 2 I want a matrix of characters with "window" columns filled with "v" by filling a row, then shifting over "shift" and continuing to the next row until "v" is exhausted. You can assume "v" will evenly fit "m" so the result needs t...