search for: shamt

...not. Any thoughts on how to best handle these cases? For the shifts I could obviously introduce a target-specific SelectionDAG node, but then I'd lose the benefit of most of the target-independent DAG combines. A target DAG combine could custom lower the shift amount. e.g. converting (shl val, shamt) to (shl val, (and shamt, 31)) before it gets widened to i64. But this runs the risk of introducing an unnecessary AND operation if it turns out that the SelectionDAG node is transformed by the time it reaches instruction selection. So for this particular issue with shifts, introducing a target-spe...

...::SUB, dl, ShTy, NVBitsNode, Amt); SDValue Cmp = DAG.getSetCC(dl, TLI.getSetCCResultType(ShTy), Amt, NVBitsNode, ISD::SETULT); SDValue Lo1, Hi1, Lo2, Hi2; switch (N->getOpcode()) { default: llvm_unreachable("Unknown shift"); case ISD::SHL: // ShAmt < NVTBits Lo1 = DAG.getConstant(0, NVT); // Low part is zero. Hi1 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); // High part from Lo part. // ShAmt >= NVTBits Lo2 = DAG.getNode(ISD::SHL, dl, NVT, InL, Amt); Hi2 = DAG.getNode(ISD::OR, dl, NVT,...

...est handle these cases? For the shifts I could > > obviously introduce a target-specific SelectionDAG node, but then I'd lose the > > benefit of most of the target-independent DAG combines. A target DAG combine > > could custom lower the shift amount. e.g. converting (shl val, shamt) to (shl > > val, (and shamt, 31)) before it gets widened to i64. But this runs the risk > > of introducing an unnecessary AND operation if it turns out that the > > SelectionDAG node is transformed by the time it reaches instruction selection. > > So for this particular iss...

...On Mon, Feb 25, 2019 at 1:12 PM Nuno Lopes <nunoplopes at sapo.pt> wrote: > Thanks Sanjay! > > I did a quick study of these funnel shifts: > The generic lowering to SDAG is correct for the optimization below. It > actually stops poison if shift amount is zero: > SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC); > (...) > SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ); > setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or)); > > This is assuming select in SDAG stops poison in the same way we&...

...On Mon, Feb 25, 2019 at 1:12 PM Nuno Lopes <nunoplopes at sapo.pt> wrote: > Thanks Sanjay! > > I did a quick study of these funnel shifts: > The generic lowering to SDAG is correct for the optimization below. It > actually stops poison if shift amount is zero: > SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC); > (...) > SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, ISD::SETEQ); > setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : Y, Or)); > > This is assuming select in SDAG stops poison in the same way we&...

There's a question about the behavior of funnel shift [1] + select and poison here that reminds me of previous discussions about select and poison [2]: https://github.com/AliveToolkit/alive2/pull/32#discussion_r257528880 Example: define i8 @fshl_zero_shift_guard(i8 %x, i8 %y, i8 %sh) { %c = icmp eq i8 %sh, 0 %f = fshl i8 %x, i8 %y, i8 %sh %s = select i1 %c, i8 %x, i8 %f ; shift amount is 0

...t sapo.pt>> wrote: > > Thanks Sanjay! > > > > I did a quick study of these funnel shifts: > > The generic lowering to SDAG is correct for the optimization below. > It > > actually stops poison if shift amount is zero: > > SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC); > > (...) > > SDValue IsZeroShift = DAG.getSetCC(sdl, CCVT, ShAmt, Zero, > > ISD::SETEQ); > > setValue(&I, DAG.getSelect(sdl, VT, IsZeroShift, IsFSHL ? X : > > Y, Or)); > > > &g...

...DNode op, bits<6> func, string instr_asm, InstrItinClass itin, RegisterClass RC, list<Register> DefRegs>: FR<0x00, func, (outs), (ins RC:$rs, RC:$rt), !strconcat(instr_asm, "\t$$zero, $rs, $rt"), [(op RC:$rs, RC:$rt)], itin> { let rd = 0; let shamt = 0; let Defs = DefRegs; } Note:,there doesn't seem to be an issue with the 32 bit versions which seem to be the following the same pattern. Also, the 64 bit version is in its' own td, though I don't know why that would matter. class Div32<SDNode op, bits<6> func, string i...

...nstr_asm, SDNode OpNode, InstrItinClass itin, RegisterClass RC, bit isComm = 0>: FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt), !strconcat("+$rd=$rs ",!strconcat(instr_asm, " $rt")), [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> { let shamt = 0; let isCommutable = isComm; let isReMaterializable = 1; } This works, but I have to have the whitespace after $rs (which isn't supported). If I get rid of the space, I get a message like "ArithLogicR doesn't have operand $rsAND" or something similar. The point is that i...

...========================================================= >> --- llvm/trunk/test/CodeGen/X86/shift-bmi2.ll (original) >> +++ llvm/trunk/test/CodeGen/X86/shift-bmi2.ll Tue Oct 15 18:33:07 2013 >> @@ -30,10 +30,11 @@ entry: >> %x = load i32* %p >> %shl = shl i32 %x, %shamt >> ; BMI2: shl32p >> -; BMI2: shlxl %{{.+}}, ({{.+}}), %{{.+}} >> +; Source order scheduling prevents folding, rdar:14208996. >> +; BMI2: shlxl %{{.+}}, %{{.+}}, %{{.+}} >> ; BMI2: ret >> ; BMI264: shl32p >> -; BMI264: shlxl %{{.+}}, ({{.+}}), %{{.+}} >&...

On Wed, May 20, 2009 at 4:55 PM, Dan Gohman <gohman at apple.com> wrote: > Can you explain why you chose the approach of using a new pass? > I pictured removing LegalizeDAG's type legalization code would > mostly consist of finding all the places that use TLI.getTypeAction > and just deleting code for handling its Expand and Promote. Are you > anticipating something more

On May 20, 2009, at 1:34 PM, Eli Friedman wrote: > On Wed, May 20, 2009 at 1:19 PM, Eli Friedman > <eli.friedman at gmail.com> wrote: > >> Per subject, this patch adding an additional pass to handle vector >> >> operations; the idea is that this allows removing the code from >> >> LegalizeDAG that handles illegal types, which should be a significant

...SDValue &Lo, SDValue &Hi, - DebugLoc dl) { - assert((Opc == ISD::SHL || Opc == ISD::SRA || Opc == ISD::SRL) && - "This is not a shift!"); - - MVT NVT = TLI.getTypeToTransformTo(Op.getValueType()); - SDValue ShAmt = LegalizeOp(Amt); - MVT ShTy = ShAmt.getValueType(); - unsigned ShBits = ShTy.getSizeInBits(); - unsigned VTBits = Op.getValueType().getSizeInBits(); - unsigned NVTBits = NVT.getSizeInBits(); - - // Handle the case when Amt is an immediate. - if (ConstantSDNode *CN = dyn_cast<ConstantSDNo...