search for: sgpr_32

...ng the subreg indices into the wrong classes but it would also make it harder to define the register banks. > I'm a little confused about what the issue is. AMDGPU has 2 64-bit register classes each with sub0 and sub1 sub-registers: VReg_64:sub0=VGPR_32 VReg_64:sub1=VGPR_32 SReg_64:sub0=SGPR_32 SReg_64:sub1=SGPR_32 Are you saying that tablegen considers VReg_64:sub0 and SReg_64:sub0 to be the same sub-register class because they are both called sub0 ? -Tom >> On 10 May 2017, at 21:58, Daniel Sanders via llvm-dev <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.or...

...load clustering. I restrict load clustering to 4 at a time, but when I look at the debug output, the loads are always being scheduled based on the fact that that are clustered. e.g. Pick Top CLUSTER Scheduling SU(10) %vreg13<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 4; mem:LD4[<unknown>] SGPR_32:%vreg13 SReg_128:%vreg9 I have a feeling there is something wrong with my machine model in the R600 backend, but I've experimented with a few variations of it and have been unable to solve this problem. Does anyone have any idea what I might be doing wrong? Here are my resource definitions f...

...> to 4 at a time, but when I look at the debug output, the loads are > > always being scheduled based on the fact that that are clustered. e.g. > > > > Pick Top CLUSTER > > Scheduling SU(10) %vreg13<def> = S_BUFFER_LOAD_DWORD_IMM %vreg9, 4; mem:LD4[<unknown>] SGPR_32:%vreg13 SReg_128:%vreg9 > > Well, only 4 loads in a sequence should have the “cluster” edges. You should be able to see that when the DAG is printed before scheduling. > There are 4 consecutive 'Pick Top CLUSTER' then a 'Pick Top WEAK' and then the pattern repeats itself...

Hi Tom, The output: Added VReg_64(explicit) Added VS_32(explicit (VS_32) VReg_64 class-with-subregs: VReg_64) is saying that VS_32 was added because VReg_64 was explicitly specified and that while inspecting VS_32, it noticed that every register in VS_32 was a subregister of a register from VReg_64 using a single common subregister index. I've added some more tracing to my local copy and