Displaying 6 results from an estimated 6 matches for "sgpr32".
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gpr32
2019 Aug 27
2
TargetRegisterInfo::getCommonSubClass bug, perhaps.
Hi,
ABCRegister.td :
def SGPR32 : RegisterClass<"ABC", [i32], 16, (add
S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
S12, S13, S14, S15
)>;
def SFGPR32 : RegisterClass<"ABC", [f32], 16, (add
S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11,
S12, S13, S14, S15
)>;
===== Ins...
2019 Nov 25
2
Tablegen PAT limitation?
...ey don’t have them. The error you saw (“rs1 must be an identifier”) was caused by tablegen being unable to match the rs1 in the pattern with any of the instruction operands.
Could you change the pattern to
[(OpNode (v1i16 MGPR:$rs1), (add (v1i32 (bitconvert (i32 SGPR32:$rbase))), (shl (v1i32 (sext (v1i16 MGPR:$roffset))), (v1i32 (build_vector (i32 uimm2:$rshift))) )))]
--
Krzysztof Parzyszek kparzysz at quicinc.com AI tools development
From: Celine <595602881 at qq.com>
Sent: Thursday...
2019 Nov 22
2
Tablegen PAT limitation?
...amespace = "";
list<Predicate> Predicates = [];
string DecoderMethod = "";
bit hasCompleteDecoder = 1;
string Namespace = "RPP";
dag OutOperandList = (outs);
dag InOperandList = (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift);
string AsmString = "STORE $rs1, [$rbase + ( $roffset << $rshift )]";
list<dag> Pattern = [(store (v1i16 ?:$rs1), (add (v1i32 (bitconvert (i32 ?:$rbase))), (shl (v1i32 (sext (v1i16 ?:$roffset))), (v1i32 (build_vec...
2019 Nov 21
2
Tablegen PAT limitation?
Hi Krzysztof,
Today I try it on llvm9.0.0 version.
def bos : RPPInstMMEMrr<OPC_STORE,
(outs), (ins MGPR:$rs1, SGPR32:$rbase, MGPR:$roffset, uimm2:$rshift),
!strconcat(opcodestr, ""), "$rs1, [$rbase + ( $roffset << $rshift )]",
// &nb...
2019 Nov 20
4
Tablegen PAT limitation?
...16, (add
IA, IB, IC, ID, IE, IF, IG, IH
)>;
def MGPR : RegisterClass<"ABC", [v1i16, v1f16], 16, (add
IA, IB, IC, ID, IE, IF, IG, IH
)>;
def SGPR32 : RegisterClass<"ABC", [ i32, f32 ], 32, (add
DS0, DS1, DS2, DS3, DS4, DS5, DS6, DS7, DS8, DS9, DS10,DS11,
DS12, DS13, DS14, DS15...
2019 Sep 27
2
Maybe a TableGen bug?
...2}, roffset{1}, roffset{0}, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
field bits<32> SoftFail = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
string Namespace = "ABC";
dag OutOperandList = (outs GPR_OUT:$rs1);
dag InOperandList = (ins SGPR32:$rbase, MGPR_ST:$roffset, uimm2:$rshift);
string AsmString = "LOAD [$rbase + ( $roffset << $rshift )], $rs1";
list<dag> Pattern = [(set i16v:$rs1, (load (add i32:$rbase, (shl (*sext
(i16 (bitconvert i16v:$roffset))*), i32:$rshift))))];
.....
i16v is a new type we added, sa...