Displaying 20 results from an estimated 53 matches for "gpr32".
2018 Dec 05
2
Strange regalloc behaviour: one more available register causes much worse allocation
...arily keeping an extra
register live across the JumpTableDest8).
What's going on
---------------
What this block looks like after live range splitting has happened is:
7352B bb.17.switchdest13:
; predecessors: %bb.3
successors: %bb.30(0x80000000); %bb.30(100.00%)
7360B %390:gpr32 = COPY $wzr
7364B %434:gpr64 = COPY %432:gpr64
7368B %429:gpr32 = COPY %427:gpr32
7376B %424:gpr32 = COPY %422:gpr32
7384B %419:gpr32 = COPY %417:gpr32
7392B %414:gpr32 = COPY %412:gpr32
7400B %409:gpr32 = COPY %407:gpr32
7408B %404:gpr32 = COPY %402:gpr32
7416B %399...
2018 Dec 05
3
Strange regalloc behaviour: one more available register causes much worse allocation
...eping an extra
register live across the JumpTableDest8).
What's going on
---------------
What this block looks like after live range splitting has happened is:
7352B bb.17.switchdest13:
; predecessors: %bb.3
successors: %bb.30(0x80000000); %bb.30(100.00%)
7360B %390:gpr32 = COPY $wzr
7364B %434:gpr64 = COPY %432:gpr64
7368B %429:gpr32 = COPY %427:gpr32
7376B %424:gpr32 = COPY %422:gpr32
7384B %419:gpr32 = COPY %417:gpr32
7392B %414:gpr32 = COPY %412:gpr32
7400B %409:gpr32 = COPY %407:gpr32
7408B %404:gpr32 = COPY %402:gpr32
7416B %399...
2012 May 11
2
[LLVMdev] TableGen pattern for negated operand
...subset), not just MUL, with a FNEG'd operand? I expect I can
define a PatFrag:
def fneg_su : PatFrag<(ops node:$val), (fneg node:$val), [{ return
N->hasOneUse(); }]>;
and then use that in each target instruction patten in XXXInstrInfo.td, such as:
def XXX_MUL : XXXInst<
(outs GPR32:$dst),
(ins GPR32:$src1, GPR32:$src2),
"mul $dst, -$src1, $src2",
[(set $dst, (mul (fneg_su GPR32:$src1), GPR32:$src2))]>;
but I would like to believe there's a way to do this with a Pattern<>
definition instead, with help from PatFrag and the SDNode_XFORM
perhaps....
2012 May 11
0
[LLVMdev] TableGen pattern for negated operand
...stom
nodes if it meets that condition. But I think a better solution would be
to add pattern matching rules for all of them systematically. IMO it's
cleaner and easier to maintain. You can use multiclasses :
multiclass Inst< node op, string opc> {
def _rr : Instruction<(outs GPR32:$dst), (ins GPR32:$src1,
GPR32:$src2),
"!strcat(opc, " $dst, $src1, $src2")",
[(set $dst, (op GPR32:$src1, GPR32:$src2))]>;
def _fneg_rr : Instruction<(outs GPR32:$dst), (ins GPR32:$src1,
GPR32:$src2),
"!strcat(opc, " $dst,...
2013 Apr 12
1
[LLVMdev] Problem with Store of i8 in a global address
...:CONST32", SDTmyCONST32>;
def myCONST32_GP : SDNode<"myISD::CONST32_GP", SDTmyCONST32>;
let PrintMethod = "printDMemOperand" in
def globaladdress : Operand<i32>;
def STdb : STInst<(outs),
(ins globaladdress:$addr, GPR32:$ra),
"stdb\t$addr, $ra",
[],
IIStore>
{
let mayStore = 1;
}
def : Pat<(atomic_store_8 (IcyflexCONST32_GP tglobaladdr:$global),
(i32 GPR32:$ra)),
(STdb...
2017 Oct 25
3
How vregs are assigned to operands in IR
...* %z, align 4
%2 = load i32, i32* %z, align 4
%call = call i32 (i8*, ...) @printf(i8* getelementptr inbounds ([18
x i8], [18 x i8]* @.str, i32 0, i32 0), i32 %2)
ret i32 0
}
Generated machine instructions (initial)
BB#0: derived from LLVM BB %entry
%vreg11<def> = MOVi32imm 6; GPR32:%vreg11
%vreg12<def> = MOVi32imm 5; GPR32:%vreg12
STRWui %WZR, <fi#0>, 0; mem:ST4[FixedStack0]
STRWui %vreg12, <fi#1>, 0; mem:ST4[FixedStack1] GPR32:%vreg12
STRWui %vreg11, <fi#2>, 0; mem:ST4[FixedStack2] GPR32:%vreg11
...........................
2012 Sep 05
5
[LLVMdev] 64 bit special purpose registers
...; def R2 : Register<2>;
> def R3 : Register<1>;
> def R4 : Register<2>;
> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>
> This says that D1 is a register with two components, lo and hi. When you
> allocate D1, you also use R1/R2.
> def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))>
> ...
> def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;
>
> So in your instruction it would be something like:
> def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0, GPR32:$src1), ...>...
2012 Aug 07
0
[LLVMdev] 64 bit special purpose registers
...gIndex;
def R1 : Register<1>;
def R2 : Register<2>;
def R3 : Register<1>;
def R4 : Register<2>;
def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
This says that D1 is a register with two components, lo and hi. When you allocate D1, you also use R1/R2.
def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))> ...
def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;
So in your instruction it would be something like:
def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0, GPR32:$src1), ...>;
This would mean you...
2012 Aug 06
2
[LLVMdev] 64 bit special purpose registers
On Mips 32 there is traditionally a 64 bit HI/LO register for the result
of multiplying two 64 bit numbers.
There are corresponding instructions to load the LO and HI parts into
individual 32 registers.
On Mips with the DSP ASE (an application specific extension), there are
actual 4 such pairs of
registers.
Is there a way to have special purpose 64 bit registers without actually
having to
2012 Sep 06
0
[LLVMdev] 64 bit special purpose registers
...>;
> def R3 : Register<1>;
> def R4 : Register<2>;
> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>
> This says that D1 is a register with two components, lo and hi.
> When you allocate D1, you also use R1/R2.
> def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u",
> 1, 4))> ...
> def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;
>
> So in your instruction it would be something like:
> def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0, GPR3...
2018 Jan 04
2
Canonical way to handle zero registers?
..., Jan 2, 2018 at 8:28 AM, Daniel Sanders <daniel_l_sanders at apple.com>
wrote:
> Hi Sean,
>
> Just to give the GlobalISel perspective on this,
Thanks for chiming in!
> GlobalISel supports the declaration of a zero register in the register
> class like so:
> def GPR32z : RegisterOperand<GPR32> {
> let GIZeroRegister = WZR;
> }
> With that definition, the tablegen-erated ISel code will try to replace
> will try to replace 'G_CONSTANT s32 0' with WZR whenever the operand is
> specified as GPR32z.
>
Is this method...
2012 Sep 05
0
[LLVMdev] 64 bit special purpose registers
...gIndex;
def R1 : Register<1>;
def R2 : Register<2>;
def R3 : Register<1>;
def R4 : Register<2>;
def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
This says that D1 is a register with two components, lo and hi. When you allocate D1, you also use R1/R2.
def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))> ...
def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;
So in your instruction it would be something like:
def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0, GPR32:$src1), ...>;
This would mean you...
2012 Sep 07
1
[LLVMdev] 64 bit special purpose registers
...;
>> def R3 : Register<1>;
>> def R4 : Register<2>;
>> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>>
>> This says that D1 is a register with two components, lo and hi. When you
>> allocate D1, you also use R1/R2.
>> def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))>
>> ...
>> def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;
>>
>> So in your instruction it would be something like:
>> def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0,...
2018 Jan 04
0
Canonical way to handle zero registers?
...sanders at apple.com <mailto:daniel_l_sanders at apple.com>> wrote:
> Hi Sean,
>
> Just to give the GlobalISel perspective on this,
>
> Thanks for chiming in!
>
> GlobalISel supports the declaration of a zero register in the register class like so:
> def GPR32z : RegisterOperand<GPR32> {
> let GIZeroRegister = WZR;
> }
> With that definition, the tablegen-erated ISel code will try to replace will try to replace 'G_CONSTANT s32 0' with WZR whenever the operand is specified as GPR32z.
>
>
> Is this method...
2012 Sep 06
3
[LLVMdev] 64 bit special purpose registers
...Register<1>;
>> def R4 : Register<2>;
>> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>>
>> This says that D1 is a register with two components, lo and hi.
>> When you allocate D1, you also use R1/R2.
>> def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u",
>> 1, 4))> ...
>> def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;
>>
>> So in your instruction it would be something like:
>> def mul : Inst<(dst GPR64:$dst), (s...
2012 Sep 06
0
[LLVMdev] 64 bit special purpose registers
...;
>> def R3 : Register<1>;
>> def R4 : Register<2>;
>> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
>>
>> This says that D1 is a register with two components, lo and hi. When you
>> allocate D1, you also use R1/R2.
>> def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1, 4))>
>> ...
>> def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;
>>
>> So in your instruction it would be something like:
>> def mul : Inst<(dst GPR64:$dst), (src GPR32:$src0,...
2013 Jun 24
1
[LLVMdev] DebugInfo: Missing non-trivially-copyable parameters in SelectionDAG
...LDR <fi#-1>, 0; mem:LD8[FixedStack-1](align=16) GPR64:%vreg16
%vreg17<def> = MOVZxii 42, 0; GPR64:%vreg17
LS64_STR %vreg17<kill>, <fi#-2>, 0; mem:ST8[FixedStack-2](align=16) GPR64:%vreg17
%vreg19<def> = IMPLICIT_DEF; GPR64:%vreg19
%vreg20<def> = IMPLICIT_DEF; GPR32:%vreg20
%vreg18<def,tied1> = INSERT_SUBREG %vreg19<tied0>, %vreg20<kill>, sub_32; GPR64:%vreg18,%vreg19 GPR32:%vreg20
%X0<def> = COPY %vreg18; GPR64:%vreg18
%X1<def> = COPY %vreg18; GPR64:%vreg18
%X2<def> = COPY %vreg18; GPR64:%vreg18
%X3<def> = COPY %...
2012 Sep 07
1
[LLVMdev] 64 bit special purpose registers
...t;1>;
> >> def R4 : Register<2>;
> >> def D1 : RegisterWithSubRegs<1, [R1, R2], [lo_comp, hi_comp]>;
> >>
> >> This says that D1 is a register with two components, lo and hi. When you
> >> allocate D1, you also use R1/R2.
> >> def GPR32 : RegisterClass<..., [i32], [32], (add (sequence "R%u", 1,
> 4))>
> >> ...
> >> def GPR64 : RegisterClass<..., [i64], [64], (add D1)> ...;
> >>
> >> So in your instruction it would be something like:
> >> def mul : Inst<(dst G...
2014 Jun 11
2
[LLVMdev] Help regarding ad new functionality in Backend
Dear,
I am looking at the Instructions defined in the XXXXInstrInfo.td where I
can see a def record defined like below
def ADD8rr : I8rr<0x0,
(outs GR8:$dst), (ins GR8:$src, GR8:$src2),
"add.b\t{$src2, $dst}",
[(set GR8:$dst, (*add *GR8:$src, GR8:$src2)),
(implicit SRW)]>;
Now here I would like the to
2018 Jan 02
0
Canonical way to handle zero registers?
Hi Sean,
Just to give the GlobalISel perspective on this, GlobalISel supports the declaration of a zero register in the register class like so:
def GPR32z : RegisterOperand<GPR32> {
let GIZeroRegister = WZR;
}
With that definition, the tablegen-erated ISel code will try to replace will try to replace 'G_CONSTANT s32 0' with WZR whenever the operand is specified as GPR32z.
> On 21 Dec 2017, at 21:22, Sean Silva via llvm-dev <...