Displaying 3 results from an estimated 3 matches for "sextloadv2i8".
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2012 Oct 30
2
[LLVMdev] how to define extending vector load patterns?
I have an operation which loads a 16 bit block of data as 2 8-bit
elements, sign extends the both parts to 32 bits and stores the result
into 64-bit vector register.
How can I define the pattern for this?
just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]
gives me error that extloav2i8 is not defined.
(the same principle works for scalar sextload)
So I need to define it from the SDNodes? But how? there is no SDNode for
extload? it's load with some extra parameters?
2012 Oct 30
0
[LLVMdev] how to define extending vector load patterns?
Hi Heikki,
> just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]
>
> gives me error that extloav2i8 is not defined.
I don't have a target to test this on, but looking at
include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8"
PatFrag, at least. I'd suggest a pattern along the lines of:
(set V2I32Regs:$res...
2012 Oct 30
1
[LLVMdev] how to define extending vector load patterns?
On 10/30/2012 04:52 PM, Tim Northover wrote:
> Hi Heikki,
>
>> just using [(set V2I32Regs:$result, (sextloadv2i8 ADDRrr:$address))]
>>
>> gives me error that extloav2i8 is not defined.
>
> I don't have a target to test this on, but looking at
> include/llvm/Target/TargetSelectionDAG.td, there is an "sextloadvi8"
> PatFrag, at least. I'd suggest a pattern along the lin...