Displaying 6 results from an estimated 6 matches for "sextloadi8".
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zextloadi8
2019 Sep 10
2
tablegen exponential behavior
...(mulBz<ldop> GPR64sp:$Rn, GPR64sp:$Rm))))),
(EXTRACT_SUBREG
(i64 (DOT (DUPv2i32gpr WZR),
(v8i8 (LD1Onev8b GPR64sp:$Rn)),
(v8i8 (LD1Onev8b GPR64sp:$Rm)))),
sub_32)>, Requires<[HasDotProd]>;
def : DotProductI32<SDOTv8i8, sextloadi8>;
def : DotProductI32<UDOTv8i8, zextloadi8>;
Then when I extended it to 8 element vectors, the time spent by tblgen exploded:
from under 7 seconds (on A-72) on the AArch64 td files and the above patch
to more than half an hour when I decided to terminate the processes.
Here are the add...
2011 Jun 23
0
[LLVMdev] Instr Description Problem of MCore Backend
Hello
> Finally, I don't know how to describe following instructions in
> MCoreInstrInfo.td, because of its variable ins/outs. Or what other files
> should I use to finish this description?
Do you need the isel support for them? If yes, then you should custom
isel them. iirc ARM and SystemZ backends have similar instructions,
while only the first one supports full isel for them. In
2013 May 23
3
[LLVMdev] Definition of RegisterClass for load instruction in Thumb2
...rGPR, t2LDRSB_PRE uses GPR. I wonder if lr and pc are already prevented from being allocated in pre-indexing case, because of some register hint that is being enforced?
defm t2LDRSB : T2I_ld<1, 0b00, "ldrsb", IIC_iLoad_bh_i, IIC_iLoad_bh_si,
rGPR, UnOpFrag<(sextloadi8 node:$Src)>>;
def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb),
(ins t2addrmode_imm8:$addr),
AddrModeT2_i8, IndexModePre, IIC_iLoad_bh_iu,
"ldrsb", "\t$Rt, $addr!&q...
2012 Apr 19
0
[LLVMdev] Target Dependent Hexagon Packetizer patch
...dedComplexity = 10, isPredicable = 1 in
>> def LDrib_indexed_V4 : LDInst<(outs IntRegs:$dst),
>> (ins IntRegs:$src1, IntRegs:$src2),
>> "$dst=memb($src1+$src2<<#0)",
>> - [(set IntRegs:$dst, (sextloadi8 (add IntRegs:$src1,
>> - IntRegs:$src2)))]>,
>> + [(set (i32 IntRegs:$dst),
>> + (i32 (sextloadi8 (add (i32 IntRegs:$src1),
>> +...
2011 Jun 23
2
[LLVMdev] Instr Description Problem of MCore Backend
Hi, all:
Now I'm working on writing a backend for Moto MCore, but I don't know how to
describe some instructions.
First, I've already written MCoreRegisterInfo.td like these:
class MCoreReg<bits<4> num, string name> : Register<name> {
let Namespace = "MCore";
field bits<4> Num = num;
}
def R0 : MCoreReg< 0, "R0">,
2016 Apr 27
2
[Sparc] builtin setjmp / longjmp - need help to get past last problem
...tr),
+ "#EH_SjLj_Setup\t$ptr", []>,
+ Requires<[Is32Bit]>;
+ }
+
// Section B.1 - Load Integer Instructions, p. 90
let DecoderMethod = "DecodeLoadInt" in {
defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
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