Displaying 20 results from an estimated 76 matches for "setsrc".
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2015 Jan 09
3
[RESEND/PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...res.data.u16 = util_iround(CLAMP(imm0.reg.data.f64, 0,
+ UINT16_MAX));
+ else
+ res.data.u16 = util_iround(imm0.reg.data.f64);
+ break;
+ default:
+ return;
+ }
+ i->setSrc(0, bld.mkImm(res.data.u16));
+ break;
+ case TYPE_U32:
+ switch (i->sType) {
+ case TYPE_F32:
+ if (i->saturate)
+ res.data.u32 = util_iround(CLAMP(imm0.reg.data.f32, 0,
+ UINT32_MAX));
+...
2015 Jan 10
2
[PATCH v2] nv50/ir: Handle OP_CVT when folding constant expressions
...res.data.u16 = util_iround(CLAMP(imm0.reg.data.f32, 0,
+ UINT16_MAX));
+ else
+ res.data.u16 = util_iround(imm0.reg.data.f32);
+ break;
+ default:
+ return;
+ }
+ i->setSrc(0, bld.mkImm(res.data.u16));
+ break;
+ case TYPE_U32:
+ switch (i->sType) {
+ case TYPE_F32:
+ if (i->saturate)
+ res.data.u32 = util_iround(CLAMP(imm0.reg.data.f32, 0,
+ UINT32_MAX));
+...
2014 Jul 05
1
[PATCH v4] nv50/ir: Handle OP_CVT when folding constant expressions
...res.data.u16 = (conv < 0) ? 0 : CLAMP((uint32_t)conv, 0,
+ UINT16_MAX);
+ }
+ else res.data.u16 = util_iround(imm0.reg.data.f64);
+ break;
+ default:
+ return;
+ }
+ i->setSrc(0, bld.mkImm(res.data.u16));
+ break;
+ case TYPE_U32:
+ switch (i->sType) {
+ case TYPE_F32:
+ if (i->saturate) {
+ int32_t conv = util_iround(imm0.reg.data.f32);
+ res.data.u32 = (conv < 0) ? 0 : CLAMP((uint32_t)conv, 0,...
2014 Aug 08
2
[PATCH 1/3] nvc0/ir: add base tex offset for fermi indirect tex case
...ering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -603,10 +603,18 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
Value *ticRel = i->getIndirectR();
Value *tscRel = i->getIndirectS();
- if (ticRel)
+ if (ticRel) {
i->setSrc(i->tex.rIndirectSrc, NULL);
- if (tscRel)
+ if (i->tex.r)
+ ticRel = bld.mkOp2v(OP_ADD, TYPE_U32, bld.getScratch(),
+ ticRel, bld.mkImm(i->tex.r));
+ }
+ if (tscRel) {
i->setSrc(i->tex.sIndirectSrc, NULL);
+...
2014 Jul 03
0
[PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...tch(i->dType) {
+ case TYPE_U16:
+ switch (i->sType) {
+ case TYPE_F32: res.data.u16 = util_iround(imm0.reg.data.f32); break;
+ case TYPE_F64: res.data.u16 = util_iround(imm0.reg.data.f64); break;
+ default:
+ return;
+ }
+ i->setSrc(0, bld.mkImm(res.data.u16));
+ break;
+ case TYPE_U32:
+ switch (i->sType) {
+ case TYPE_F32: res.data.u32 = util_iround(imm0.reg.data.f32); break;
+ case TYPE_F64: res.data.u32 = util_iround(imm0.reg.data.f64); break;
+ default:
+ return;...
2015 May 09
2
[PATCH 3/4] nvc0/ir: optimize set & 1.0 to produce boolean-float sets
...;
> + if (i->src(t).mod != Modifier(0)) {
> + assert(i->src(t).mod == Modifier(NV50_IR_MOD_NOT));
> + i->src(t).mod = Modifier(0);
> + cmp->setCond = reverseCondCode(cmp->setCond);
> + }
> + i->op = OP_MOV;
> + i->setSrc(s, NULL);
> + if (t) {
> + i->setSrc(0, i->getSrc(t));
> + i->setSrc(t, NULL);
> + }
> + }
> + break;
> +
> case OP_SHL:
> {
> if (s != 1 || i->src(0).mod != Modifier(0))
> diff --git a/src/gallium/drive...
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
...if (imm0.reg.data.f32 != 1.0)
- return;
- if (i->getSrc(t)->getInsn()->dType != TYPE_U32)
- return;
+ Instruction *src = i->getSrc(t)->getInsn();
+ ImmediateValue imm1;
+ if (imm0.reg.data.u32 == 0) {
+ i->op = OP_MOV;
+ i->setSrc(0, new_ImmediateValue(prog, 0u));
+ i->src(0).mod = Modifier(0);
+ i->setSrc(1, NULL);
+ } else if (imm0.reg.data.u32 == ~0U) {
+ i->op = i->src(t).mod.getOp();
+ if (t) {
+ i->setSrc(0, i->getSrc(t));
+ i->src(0).mod =...
2015 Jan 01
0
[PATCH] nv50/ir: fold MAD when one of the multiplicands is const
...b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -784,6 +784,26 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
i->src(1).mod = 0;
}
break;
+ case OP_MAD:
+ if (imm0.isInteger(0)) {
+ i->op = OP_MOV;
+ i->setSrc(0, i->getSrc(2));
+ i->setSrc(1, NULL);
+ i->setSrc(2, NULL);
+ } else
+ if (imm0.isInteger(1) || imm0.isInteger(-1)) {
+ if (imm0.isNegative())
+ i->src(t).mod = i->src(t).mod ^ Modifier(NV50_IR_MOD_NEG);
+ if (s == 0) {
+...
2016 Oct 02
2
[PATCH] nv50/ir: Propagate third immediate src when folding OP_MAD
...au/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1008,13 +1008,22 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
break;
case OP_MAD:
if (imm0.isInteger(0)) {
+ ImmediateValue imm1;
i->setSrc(0, i->getSrc(2));
i->src(0).mod = i->src(2).mod;
i->setSrc(1, NULL);
i->setSrc(2, NULL);
- i->op = i->src(0).mod.getOp();
- if (i->op != OP_CVT)
- i->src(0).mod = 0;
+ if (i->src(0).getImmediate(imm1)) {...
2014 Jul 06
0
[PATCH v5] nv50/ir: Handle OP_CVT when folding constant expressions
...res.data.u16 = util_iround(CLAMP(imm0.reg.data.f64, 0,
+ UINT16_MAX));
+ else
+ res.data.u16 = util_iround(imm0.reg.data.f64);
+ break;
+ default:
+ return;
+ }
+ i->setSrc(0, bld.mkImm(res.data.u16));
+ break;
+ case TYPE_U32:
+ switch (i->sType) {
+ case TYPE_F32:
+ if (i->saturate)
+ res.data.u32 = util_iround(CLAMP(imm0.reg.data.f32, 0,
+ UINT32_MAX));
+...
2015 Jan 11
0
[PATCH v2] nv50/ir: Handle OP_CVT when folding constant expressions
...n't fit in the
destination... whether it saturates or not. I don't hugely care
though.
> + else
> + res.data.u16 = util_iround(imm0.reg.data.f32);
> + break;
> + default:
> + return;
> + }
> + i->setSrc(0, bld.mkImm(res.data.u16));
> + break;
> + case TYPE_U32:
> + switch (i->sType) {
> + case TYPE_F32:
> + if (i->saturate)
> + res.data.u32 = util_iround(CLAMP(imm0.reg.data.f32, 0,
> +...
2014 Jul 03
1
[PATCH v3 1/2] nv50/ir: Add support for the double Type to BuildUtil
Signed-off-by: Tobias Klausmann <tobias.johannes.klausmann at mni.thm.de>
---
.../drivers/nouveau/codegen/nv50_ir_build_util.cpp | 17 +++++++++++++++++
.../drivers/nouveau/codegen/nv50_ir_build_util.h | 2 ++
2 files changed, 19 insertions(+)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_build_util.cpp
2014 Jul 05
1
[PATCH 1/2] nvc0/ir: use manual TXD when offsets are involved
Something about how we're implementing offsets for TXD is wrong, just
flip to the generic quadop-based implementation in that case.
This is the minimal fix appropriate for backporting.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
Cc: <mesa-stable at lists.freedesktop.org>
---
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 3 ++-
1 file changed, 2
2015 Jan 10
0
[RESEND/PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...CLAMP(imm0.reg.data.f64, 0,
> + UINT16_MAX));
> + else
> + res.data.u16 = util_iround(imm0.reg.data.f64);
> + break;
> + default:
> + return;
> + }
> + i->setSrc(0, bld.mkImm(res.data.u16));
> + break;
> + case TYPE_U32:
> + switch (i->sType) {
> + case TYPE_F32:
> + if (i->saturate)
> + res.data.u32 = util_iround(CLAMP(imm0.reg.data.f32, 0,
> +...
2015 Mar 25
0
[PATCH] nv50/ir: take postFactor into account when doing peephole optimizations
...s.data.f64 = a->data.f64 * b->data.f64; break;
case TYPE_S32:
if (i->subOp == NV50_IR_SUBOP_MUL_HIGH) {
@@ -579,6 +581,7 @@ ConstantFolding::expr(Instruction *i,
i->src(0).mod = Modifier(0);
i->src(1).mod = Modifier(0);
+ i->postFactor = 0;
i->setSrc(0, new_ImmediateValue(i->bb->getProgram(), res.data.u32));
i->setSrc(1, NULL);
@@ -682,7 +685,7 @@ ConstantFolding::tryCollapseChainedMULs(Instruction *mul2,
Instruction *insn;
Instruction *mul1 = NULL; // mul1 before mul2
int e = 0;
- float f = imm2.reg.data.f32;
+ flo...
2015 Jan 11
0
[PATCH] nv50/ir: Handle OP_CVT when folding constant expressions
...res.data.u16 = util_iround(CLAMP(imm0.reg.data.f32, 0,
+ UINT16_MAX));
+ else
+ res.data.u16 = util_iround(imm0.reg.data.f32);
+ break;
+ default:
+ return;
+ }
+ i->setSrc(0, bld.mkImm(res.data.u16));
+ break;
+ case TYPE_U32:
+ assert(!i->saturate);
+ switch (i->sType) {
+ case TYPE_F32:
+ res.data.u32 = util_iround(imm0.reg.data.f32);
+ break;
+ default:
+ return;
+ }
+...
2014 Feb 19
0
[PATCH] nv50: enable cube map array texture support
...00644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -664,7 +664,7 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
bld.mkOp2(OP_MIN, TYPE_U32, src, src, bld.loadImm(NULL, 511));
i->setSrc(arg - 1, src);
}
- if (i->tex.target.isCube()) {
+ if (i->tex.target.isCube() && i->srcCount() > 4) {
std::vector<Value *> acube, a2d;
int c;
@@ -681,9 +681,10 @@ NV50LoweringPreSSA::handleTEX(TexInstruction *i)
for (c = 0...
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
...ngPass::handleTEX(TexInstruction *i)
const int sat = (i->op == OP_TXF) ? 1 : 0;
DataType sTy = (i->op == OP_TXF) ? TYPE_U32 : TYPE_F32;
bld.mkCvt(OP_CVT, TYPE_U16, layer, sTy, src)->saturate = sat;
- for (int s = dim; s >= 1; --s)
- i->setSrc(s, i->getSrc(s - 1));
- i->setSrc(0, layer);
+ if (i->op != OP_TXD || chipset < NVISA_GM107_CHIPSET) {
+ for (int s = dim; s >= 1; --s)
+ i->setSrc(s, i->getSrc(s - 1));
+ i->setSrc(0, layer);
+ } else {
+...
2015 May 09
5
[PATCH 1/4] nvc0/ir: avoid jumping to a sched instruction
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
Pretty sure there's nothing wrong with it, but it looks odd in the code.
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 2 ++
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 7 +++++--
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp | 2 ++
3 files changed, 9 insertions(+), 2 deletions(-)
2014 Jun 03
8
[PATCH v2 0/4] Constant folding of new Instructions
And another try for constant folding of Instructions for nvc0.
Please Review this!
Thanks,
Tobias Klausmann
Tobias Klausmann (4):
nvc0/ir: clear subop when folding constant expressions
nvc0/ir: Handle reverse subop for OP_EXTBF when folding constant
expressions
nvc0/ir: Handle OP_BFIND when folding constant expressions
nvc0/ir: Handle OP_POPCNT when folding constant expressions