Displaying 20 results from an estimated 94 matches for "getsrc".
2016 Apr 07
2
[PATCH] nouveau: codegen: Take src swizzle into account on loads
...- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2279,12 +2279,16 @@ Converter::handleLOAD(Value *dst0[4])
Value *off = fetchSrc(1, c);
Symbol *sym;
+ uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
+
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
off = NULL;
sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
- tgsi.getSrc(1).getValueU32(0, info) + 4 * c);
+ tgsi.getSrc(1).getValu...
2014 Dec 02
0
[PATCH RESEND] nv50/ir: use unordered_set instead of list to keep track of var defs
....cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -211,7 +211,7 @@ NV50LegalizePostRA::visit(Function *fn)
if (outWrites) {
for (std::list<Instruction *>::iterator it = outWrites->begin();
it != outWrites->end(); ++it)
- (*it)->getSrc(1)->defs.front()->getInsn()->setDef(0, (*it)->getSrc(0));
+ (*(*it)->getSrc(1)->defs.begin())->getInsn()->setDef(0, (*it)->getSrc(0));
// instructions will be deleted on exit
outWrites->clear();
}
@@ -343,7 +343,7 @@ NV50LegalizeSSA::propagate...
2016 Apr 21
3
[PATCH mesa v2 1/3] nouveau: codegen: LOAD: Always use component 0 when getting the address
...si.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2277,7 +2277,7 @@ Converter::handleLOAD(Value *dst0[4])
if (!dst0[c])
continue;
- Value *off = fetchSrc(1, c);
+ Value *off = fetchSrc(1, 0);
Symbol *sym;
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
off = NULL;
--
2.7.3
2017 Aug 12
3
[PATCH] nvc0/ir: propagate immediates to CALL input MOVs
...1572..861d08af24 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
int builtin;
bld.setPosition(i, false);
- bld.mkMovToReg(0, i->getSrc(0));
- bld.mkMovToReg(1, i->getSrc(1));
+
+ // Generate movs to the input regs for the call we want to generate
+ for (int s = 0; i->srcExists(s); ++s) {
+ Instruction *ld = i->getSrc(s)->getInsn();
+ ImmediateValue imm;
+ // check if we are moving an immediate, pro...
2017 Mar 26
5
[PATCH v5 0/5] nvc0/ir: add support for MAD/FMA PostRALoadPropagation
was "nv50/ir: PostRaConstantFolding improvements" before.
nothing really changed from the last version, just minor things.
Karol Herbst (5):
nv50/ir: restructure and rename postraconstantfolding pass
nv50/ir: implement mad post ra folding for nvc0+
gk110/ir: add LIMM form of mad
gm107/ir: add LIMM form of mad
nv50/ir: also do PostRaLoadPropagation for FMA
2016 Mar 16
2
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...t; }
> +*/
>
> // For raw loads, granularity is 4 byte.
> // Usage of the texture read mask on OP_SULDP is not allowed.
> @@ -2274,8 +2278,9 @@ Converter::handleLOAD(Value *dst0[4])
> int c;
> std::vector<Value *> off, src, ldv, def;
>
> - if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER ||
> - tgsi.getSrc(0).getFile() == TGSI_FILE_MEMORY) {
> + switch (tgsi.getSrc(0).getFile()) {
> + case TGSI_FILE_BUFFER:
> + case TGSI_FILE_MEMORY:
> for (c = 0; c < 4; ++c) {
> if (!dst0[c])
> co...
2017 Aug 13
1
[PATCH v2] nvc0/ir: propagate immediates to CALL input MOVs
...1572..7243b1d2e4 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -47,8 +47,25 @@ NVC0LegalizeSSA::handleDIV(Instruction *i)
int builtin;
bld.setPosition(i, false);
- bld.mkMovToReg(0, i->getSrc(0));
- bld.mkMovToReg(1, i->getSrc(1));
+
+ // Generate movs to the input regs for the call we want to generate
+ for (int s = 0; i->srcExists(s); ++s) {
+ Instruction *ld = i->getSrc(s)->getInsn();
+ assert(ld->getSrc(0) != NULL);
+ // check if we are moving an...
2015 May 09
2
[PATCH 3/4] nvc0/ir: optimize set & 1.0 to produce boolean-float sets
.../nv50_ir_peephole.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
> @@ -973,6 +973,35 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
> }
> break;
>
> + case OP_AND:
> + {
> + CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp();
> + if (!cmp || cmp->op == OP_SLCT)
how about if (cmp == NULL || ...) and kill the same condition later?
> + return;
> + if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
> + return;
> + if (imm0.reg.d...
2017 Apr 03
5
[PATCH v2 0/3] nv50/ir: Preapre for running Opts inside a loop
Slowly we are getting to the point, that we miss enough optimization
opportunities as the result of our own passes.
For this we need to fix AlgebraicOpt to be able to handle mods on sources
without creating new issues.
The last patch enables looping opts.
v2: update commit author
Karol Herbst (3):
nv50/ir: fix AlgebraicOpt for slcts with mods
nv50/ir: handle logops with NOT in AlgebraicOpt
2015 Jan 13
3
nv50/ir: Implement short notation for MAD V2
V2: clarify code, commit msgs, add comments. Drop code to was supposed to
make register assignment prefer SDST == SRC2 (patch 2) for now, because it
didn't quite do what I intended.
2016 Apr 07
0
[PATCH] nouveau: codegen: Take src swizzle into account on loads
...eau/codegen/nv50_ir_from_tgsi.cpp
> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
> @@ -2279,12 +2279,16 @@ Converter::handleLOAD(Value *dst0[4])
>
> Value *off = fetchSrc(1, c);
> Symbol *sym;
> + uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
> +
> if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
> off = NULL;
> sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
> - tgsi.getSrc(1).getValueU32(0, info) + 4 * c);
> +...
2016 Apr 21
0
[PATCH mesa v2 3/3] nouveau: codegen: LOAD: Take src swizzle into account
...01df4f3 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -2279,13 +2279,17 @@ Converter::handleLOAD(Value *dst0[4])
Value *off;
Symbol *sym;
+ uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
+
if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
off = NULL;
sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
- tgsi.getSrc(1).getValueU32(0, info) + 4 * c);
+ tgsi.getSrc(1).getValu...
2016 Mar 16
0
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...t size[2], uint8_t mask)
}
return n + 1;
}
+*/
// For raw loads, granularity is 4 byte.
// Usage of the texture read mask on OP_SULDP is not allowed.
@@ -2274,8 +2278,9 @@ Converter::handleLOAD(Value *dst0[4])
int c;
std::vector<Value *> off, src, ldv, def;
- if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER ||
- tgsi.getSrc(0).getFile() == TGSI_FILE_MEMORY) {
+ switch (tgsi.getSrc(0).getFile()) {
+ case TGSI_FILE_BUFFER:
+ case TGSI_FILE_MEMORY:
for (c = 0; c < 4; ++c) {
if (!dst0[c])
continue;
@@ -2295,9 +2300,12 @@ Convert...
2015 Jan 11
6
[PATCH 1/3] nv50/ir: Add support for MAD short+IMM notation
MAD IMM has a very specific SDST == SSRC2 requirement, so don't emit
Signed-off-by: Roy Spliet <rspliet at eclipso.eu>
---
.../drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp | 18 ++++++++++++------
.../drivers/nouveau/codegen/nv50_ir_target_nv50.cpp | 2 +-
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nv50.cpp
2014 Sep 01
0
[PATCH] nv50/ir: use unordered_set instead of list to keep track of var defs
....cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nv50.cpp
@@ -211,7 +211,7 @@ NV50LegalizePostRA::visit(Function *fn)
if (outWrites) {
for (std::list<Instruction *>::iterator it = outWrites->begin();
it != outWrites->end(); ++it)
- (*it)->getSrc(1)->defs.front()->getInsn()->setDef(0, (*it)->getSrc(0));
+ (*(*it)->getSrc(1)->defs.begin())->getInsn()->setDef(0, (*it)->getSrc(0));
// instructions will be deleted on exit
outWrites->clear();
}
@@ -343,7 +343,7 @@ NV50LegalizeSSA::propagate...
2014 Sep 25
0
[PATCH] gm107/ir: fix texture argument order
...sts.freedesktop.org>
---
With this, all the tex-miplevel-selection tests pass on maxwell. There is a
minor bit of this change which affects textureGrad on kepler that I have yet
to test, but I'm moderately sure it's correct and was only working by luck
before. (Changing the insbf to use getSrc(s) as its dest instead of
getSrc(0).)
.../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 32 ++++++++++++++++++----
src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 7 +++++
2 files changed, 34 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering...
2015 Aug 19
5
[PATCH 1/2] nvc0/ir: detect AND/SHR pairs and convert into EXTBF
...33..b0e74f0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1023,27 +1023,53 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
case OP_AND:
{
- CmpInstruction *cmp = i->getSrc(t)->getInsn()->asCmp();
- if (!cmp || cmp->op == OP_SLCT || cmp->getDef(0)->refCount() > 1)
- return;
- if (!prog->getTarget()->isOpSupported(cmp->op, TYPE_F32))
- return;
- if (imm0.reg.data.f32 != 1.0)
- return;
- if (i->ge...
2016 Apr 08
3
[PATCH] nouveau: codegen: Take src swizzle into account on loads
...gsi.cpp
>> +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
>> @@ -2279,12 +2279,16 @@ Converter::handleLOAD(Value *dst0[4])
>>
>> Value *off = fetchSrc(1, c);
>> Symbol *sym;
>> + uint32_t src0_component_offset = tgsi.getSrc(0).getSwizzle(c) * 4;
>> +
>> if (tgsi.getSrc(1).getFile() == TGSI_FILE_IMMEDIATE) {
>> off = NULL;
>> sym = makeSym(tgsi.getSrc(0).getFile(), r, -1, c,
>> - tgsi.getSrc(1).getValueU32(0, info) + 4 * c);
&...
2016 Mar 16
0
[PATCH mesa 6/6] nouveau: codegen: Disable more old resource handling code
...; // For raw loads, granularity is 4 byte.
>> // Usage of the texture read mask on OP_SULDP is not allowed.
>> @@ -2274,8 +2278,9 @@ Converter::handleLOAD(Value *dst0[4])
>> int c;
>> std::vector<Value *> off, src, ldv, def;
>>
>> - if (tgsi.getSrc(0).getFile() == TGSI_FILE_BUFFER ||
>> - tgsi.getSrc(0).getFile() == TGSI_FILE_MEMORY) {
>> + switch (tgsi.getSrc(0).getFile()) {
>> + case TGSI_FILE_BUFFER:
>> + case TGSI_FILE_MEMORY:
>> for (c = 0; c < 4; ++c) {
>> if (!dst0[c...
2017 Apr 03
0
[PATCH v2 1/3] nv50/ir: fix AlgebraicOpt for slcts with mods
...lium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 4c92a1efb5..bd60a84998 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1797,10 +1797,10 @@ AlgebraicOpt::handleSLCT(Instruction *slct)
if (slct->getSrc(2)->asImm()->compare(slct->asCmp()->setCond, 0.0f))
slct->setSrc(0, slct->getSrc(1));
} else
- if (slct->getSrc(0) != slct->getSrc(1)) {
+ if (slct->getSrc(0) != slct->getSrc(1) || slct->src(0).mod != slct->src(1).mod)
return;
- }
- s...