search for: getregclass

This code or subtle variations of it appears in multiple targets. It tries to convert from a register to a register class using getRegClass, but getRegClass is really supposed to take a register class enum value and get the register class object for it. It doesn't convert a register to a class. In fact there's not always a single or canonical class for a given register. What is the right way to do this? unsigned SrcReg =...

...MachineBasicBlock & mbb, unsigned src, unsigned dst ) { MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); reg_info->copyRegToReg(mbb, iter, dst, src, rc); } But the getRegClass method seems to expect a virtual register. Could someone fix this code for me? I could not find an example in the source of LLVM. Thank you...

On Sun, 2 Jul 2006, Fernando Magno Quintao Pereira wrote: > MachineBasicBlock::iterator iter = mbb.getFirstTerminator(); > const TargetRegisterClass *rc = mf.getSSARegMap()->getRegClass(dst); > const MRegisterInfo * reg_info = mf.getTarget().getRegisterInfo(); > reg_info->copyRegToReg(mbb, iter, dst, src, rc); > } > > But the getRegClass method seems to expect a virtual register. Could > someone fix this code for me? I could not find an example in the so...

...veInterval are consistent in that if allocated to a register they would all go in the same register class. Fair assumption? If I take the first LiveRange LR from LI, look up its instruction/operand at "start" and then look at its TargetOperandInfo and send TOI::RegClass to MRegisterInfo:getRegClass, is that sufficient. It seems way overly complicated. After LiveIntervalAnalysis runs we have a set of LIs we can iterate over. What's the most efficient way to get the register classes for these intervals so I know which machine registers they can go into? -Da...

...class within reason. For example, if VReg == GR32 > // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. > if (II) { > const TargetRegisterClass *DstRC = nullptr; > if (IIOpNum < II->getNumOperands()) > DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); > if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { > unsigned NewVReg = MRI->createVirtualRegister(DstRC); > if (TRI->getCommonSubClass(DstRC, > TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) What I...

...VReg == >> GR32 >> // and II requires a GR32_NOSP, just constrain VReg to GR32_NOSP. >> if (II) { >> const TargetRegisterClass *DstRC = nullptr; >> if (IIOpNum < II->getNumOperands()) >> DstRC = >> TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF)); >> if (DstRC && !MRI->constrainRegClass(VReg, DstRC, MinRCSize)) { >> unsigned NewVReg = MRI->createVirtualRegister(DstRC); >> if (TRI->getCommonSubClass(DstRC, >> TRI->getRegClass(II->OpInfo[IIOpNum].Re...

Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the SimpleValueType to define the register class instead of the actual register class defined in the td? What am I missing here? Right now, the types are bound to register classes....

...assert(!MRI->isReserved(PhysReg) && "Reserved register assignment"); Indeed there is a case where PhysReg may be a reserved physical register. Specificially, RegAllocPBQP::finalizeAlloc() may select a physical register thusly: const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg); PReg = RC.getRawAllocationOrder(MF).front(); ... VRM.assignVirt2Phys(LI.reg, PReg); The documentation for TargetRegisterClass::getRawAllocationOrder() notes that the collection may include reserved registers. So it seems that the PBQP allocator may insert a reserve physi...

David Greene wrote: > If I take the first LiveRange LR from LI, look up its > instruction/operand at "start" and then look at its > TargetOperandInfo and send TOI::RegClass to > MRegisterInfo:getRegClass, is that sufficient. > > It seems way overly complicated. Umm...yeah. That way be dragons. :-/ Fortunately, I found MachineFunction::getSSARegMap()->getRegClass(LI.reg) which works swimmingly. -Dave

...UE = mri_->use_end(); UI != UE; ) { MachineOperand &RMO = UI.getOperand(); MachineInstr *RMI = &*UI; ++UI; MachineBasicBlock *RMBB = RMI->getParent(); if (RMBB == MBB) continue; const TargetRegisterClass* RC = mri_->getRegClass(Reg); unsigned NewVReg = mri_->createVirtualRegister(RC); MachineInstrBuilder MIB = BuildMI(*RMBB, RMI, RMI->getDebugLoc(), tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg); (*MIB).getOperand(0).setIsUndef(); RMO.setReg(NewVReg)...

...porting. I agree though, it was very strange that it suddenly just changed behavior. It looks like to me that InstrEmitter.cpp:getVR is the one assigning the virtual register no? Though this code in CreateVirtualRegisters: const TargetRegisterClass *RC = TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); That returns GPRBaseRegs for RC, but it then decides to constrain it based on type: if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { const TargetRegisterClass *VTRC = TLI->getRegClassFor(Node->getSimpleValueType(i));...

...at gmail.com> wrote: >>>> >>>> Quentin, >>>> >>>> I apologize for the spamming here but in getVR (where VReg is assigned >>>> an RC), it calls: >>>> >>>> const TargetRegisterClass *RC = >>>> TLI->getRegClassFor(Op.getSimpleValueType()); >>>> VReg = MRI->createVirtualRegister(RC); >>>> >>>> My question is why is it using the SimpleValueType to define the >>>> register class instead of the actual register class defined in the td? What >>>> am...

...ing the > virtual register no? > > > No, IIRC getVR only create the virtual register for implicit defs. Which > is not your case, right? > > > Though this code in CreateVirtualRegisters: > > const TargetRegisterClass *RC = > TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); > > That returns GPRBaseRegs for RC, but it then decides to constrain it based > on type: > > if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { > const TargetRegisterClass *VTRC = > TLI->getRegClassFor(N...

...;>>> >>>>> Quentin, >>>>> >>>>> I apologize for the spamming here but in getVR (where VReg is >>>>> assigned an RC), it calls: >>>>> >>>>> const TargetRegisterClass *RC = >>>>> TLI->getRegClassFor(Op.getSimpleValueType()); >>>>> VReg = MRI->createVirtualRegister(RC); >>>>> >>>>> My question is why is it using the SimpleValueType to define the >>>>> register class instead of the actual register class defined in the td? What &gt...

> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > I'm trying to do something like this: > > // Dst = NewVReg's reg class > // *II = MCInstrDesc > // IIOpNum = II Operand Num > > if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC) > MRI->setRegClass(VReg, DstRC); > else > BuildMI(... TargetOpcode::COPY...) > > The condition is trying to reset the reg class if the DstRC reg class is valid for the operand num of the machine instruction. If the NewVReg reg...

...t; >> >> No, IIRC getVR only create the virtual register for implicit defs. Which >> is not your case, right? >> >> >> Though this code in CreateVirtualRegisters: >> >> const TargetRegisterClass *RC = >> TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF)); >> >> That returns GPRBaseRegs for RC, but it then decides to constrain it >> based on type: >> >> if (i < NumResults && TLI->isTypeLegal(Node->getSimpleValueType(i))) { >> const TargetRegisterClass *VTRC = >>...

...(2).getNode() == Node &&              User->getOperand(2).getResNo() == i) {            unsigned Reg = cast<RegisterSDNode>(User->getOperand(1))->getReg();            if (TargetRegisterInfo::isVirtualRegister(Reg)) { -            const TargetRegisterClass *RegRC = MRI->getRegClass(Reg); -            if (RegRC == RC) { +            // Allow constraining the virtual register's class within reason, +            // just like what AddRegisterOperand will allow. +            const TargetRegisterClass *ConstrainedRC +              = MRI->constrainRegClass(Reg, RC, MinRCSize...

...is how to access the machine register classes. Also, > I > > need to know which virtual register is to be mapped into each specific > > register class. I assume there is type information on the registers. I > need > > to know how to access it. > > MachineRegisterInfo::getRegClass will give you the TargetRegisterClass for > a > given virtual register. Each TargetRegisterClass has an "allocation order" > that enumerates all physical registers valid for that class. > > > And a afterthought, does LLVM place casts into > > different virtual regi...

...nd(); UI != UE; ) { > MachineOperand &RMO = UI.getOperand(); > MachineInstr *RMI = &*UI; > ++UI; > MachineBasicBlock *RMBB = RMI->getParent(); > if (RMBB == MBB) > continue; > const TargetRegisterClass* RC = mri_->getRegClass(Reg); > unsigned NewVReg = mri_->createVirtualRegister(RC); > MachineInstrBuilder MIB = > BuildMI(*RMBB, RMI, RMI->getDebugLoc(), > tii_->get(TargetInstrInfo::IMPLICIT_DEF), NewVReg); > (*MIB).getOperand(0).setIsUndef(); >...

If I have two physical registers, A and B, how do I know whether I may replace A with B in a machine instruction? My concern is that A may be in a restricted register class of which B is not a member. An example is trying to replace the x86 CL register in a shift operation. It seems like the only way to get a register class for a physical register is via