search for: sethii

..., I've had a little time to look into this now, and I think there's actually two separate problems here. By way of example, what's happening is that the following pair of MBBs: BB#315: derived from LLVM BB %bb Predecessors according to CFG: BB#314 %reg1731<def> = SETHIi 1856 %reg1732<def> = ORri %G0, 1 %reg1733<def> = SLLrr %reg1732, %reg1729 %reg1734<def> = ORri %reg1731, 1 %reg1735<def> = ANDrr %reg1733, %reg1734 %reg1736<def> = SUBCCri %reg1735, 0, %ICC<imp-def> BCOND <BB#3&g...

...med_addr global i1 declare signext i32 @lstat(i8* nocapture, %struct.stat.6.13.20.64* nocapture) #1 declare signext i32 @stat(i8* nocapture, %struct.stat.6.13.20.64* nocapture) #1 mi: | BB#0: derived from LLVM BB %entry Live Ins: %I0 %O6<def> = SAVEri %O6, -176 %I1<def> = SETHIi <ga:@Pflag>[TF=3] %I1<def> = ADDri %I1<kill>, <ga:@Pflag>[TF=4] %I1<def> = SLLXri %I1<kill>, 12 %I2<def> = LDUBri %I1<kill>, <ga:@Pflag>[TF=5]; mem:LD1[@Pflag] %I1<def> = SETHIi <ga:@stat>[TF=3] %I1<def> = ADDri %I1<k...

Hi, Chris > That is target independent code, so you should not put sparc specific changes there.  It sounds like one of the sparc-specific target hooks is wrong. Since sparc does not provide any hooks for operation of branches (e.g. AnalyzeBranch and friends) it might be possible that generic codegen code is broken in absence of these hooks. -- With best regards, Anton Korobeynikov Faculty

...t; appears that the branch delay-slots are specifically to blame here Yes, most certainly. > - the above BB#315 immediately prior to output is > > BB#7: derived from LLVM BB %bb > Live Ins: %L1 %L0 %L3 %L2 %L4 > Predecessors according to CFG: BB#6 > %L5<def> = SETHIi 1856 > %L6<def> = ORri %G0, 1 > %L3<def> = SLLrr %L6<kill>, %L3<kill> > %L5<def> = ORri %L5<kill>, 1 > %L3<def> = ANDrr %L3<kill>, %L5<kill> > %L3<def,dead> = SUBCCri %L3<kill>, 0, %I...

...Operand"; // was: let MIOperandInfo = (ops IntRegs, i32imm); let MIOperandInfo = (ops ptr_rc, i32imm); } for the C code int c; void f(void) { c = 4711; } I get the error message: Register class of operand and regclass of use don't agree! Operand = 0 Op->Val = 0x42b08d60: i32 = SETHIi 0x42b08d00 MI = STri %reg1026 VReg = 1026 VReg RegClass size = 4, align = 4 Expected RegClass size = 4, align = 4 The GlobalAddress for variable c is replaced by an ADD(HI(c), LO (c)) during lowering. I assume the code-generator cant place values in the address registers? All addres...

On Wed, Jun 26, 2013 at 3:59 PM, Nadav Rotem <nrotem at apple.com> wrote: > > On Jun 26, 2013, at 3:51 PM, Chandler Carruth <chandlerc at google.com> wrote: > > Can you suggest an alternative solution? Can you describe why you don't > think metadata is the right container? This alone isn't really helpful at > moving us toward something that there has been

...s are specifically to blame here > > Yes, most certainly. > >> - the above BB#315 immediately prior to output is >> >> BB#7: derived from LLVM BB %bb >> Live Ins: %L1 %L0 %L3 %L2 %L4 >> Predecessors according to CFG: BB#6 >> %L5<def> = SETHIi 1856 >> %L6<def> = ORri %G0, 1 >> %L3<def> = SLLrr %L6<kill>, %L3<kill> >> %L5<def> = ORri %L5<kill>, 1 >> %L3<def> = ANDrr %L3<kill>, %L5<kill> >> %L3<def,dead> = SUBCCri %L3<...

...gt; Yes, most certainly. >> >> >>> - the above BB#315 immediately prior to output is >>> >>> BB#7: derived from LLVM BB %bb >>> Live Ins: %L1 %L0 %L3 %L2 %L4 >>> Predecessors according to CFG: BB#6 >>> %L5<def> = SETHIi 1856 >>> %L6<def> = ORri %G0, 1 >>> %L3<def> = SLLrr %L6<kill>, %L3<kill> >>> %L5<def> = ORri %L5<kill>, 1 >>> %L3<def> = ANDrr %L3<kill>, %L5<kill> >>> %L3<def,dead&g...

...fo = (ops IntRegs, i32imm); > let MIOperandInfo = (ops ptr_rc, i32imm); > } > > for the C code int c; void f(void) { c = 4711; } I get the error > message: > > Register class of operand and regclass of use don't agree! > Operand = 0 > Op->Val = 0x42b08d60: i32 = SETHIi 0x42b08d00 > MI = STri %reg1026 > VReg = 1026 > VReg RegClass size = 4, align = 4 > Expected RegClass size = 4, align = 4 > > The GlobalAddress for variable c is replaced by an ADD(HI(c), LO > (c)) during lowering. I assume the code-generator cant place values >...

...MBB->end()); + sinkMBB->transferSuccessorsAndUpdatePHIs(MBB); + + MachineInstrBuilder MIB; + + unsigned LabelReg = MRI.createVirtualRegister(&SP::IntRegsRegClass); + unsigned BufReg = MI->getOperand(1).getReg(); + + MIB = BuildMI(*thisMBB, MI, DL, TII->get(SP::SETHIi)) + .addReg(LabelReg, RegState::Define) + .addMBB(sinkMBB, SparcMCExpr::VK_Sparc_HI); + MIB.setMemRefs(MMOBegin, MMOEnd); + + MIB = BuildMI(*thisMBB, MI, DL, TII->get(SP::ADDri)) + .addReg(LabelReg) + .addReg(LabelReg) + .addMBB(sin...