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...ect: [LLVMdev] changing opcode > > Is there a simple way to just change the opcode of a machine > instruction. > > I have a lot of long/short pairs where when I know the offset, i can > replace the long version with the short version. Are you looking for something like this: MI.setDesc(TII.get(NewOpcode)); This is in PPCRegisterInfo::eliminateFrameIndex. -Hal > > Tia. > > REed > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailm...

...ands::fixupUnconditionalBr(ImmBranch &Br) { MachineInstr *MI = Br.MI; MachineBasicBlock *MBB = MI->getParent(); if (!isThumb1) llvm_unreachable("fixupUnconditionalBr is Thumb1 only!"); // Use BL to implement far jump. Br.MaxDisp = (1 << 21) * 2; MI->setDesc(TII->get(ARM::tBfar)); BBInfo[MBB->getNumber()].Size += 2; adjustBBOffsetsAfter(MBB); HasFarJump = true; ++NumUBrFixed; DEBUG(dbgs() << " Changed B to long jump " << *MI); return true; }

Is there a simple way to just change the opcode of a machine instruction. I have a lot of long/short pairs where when I know the offset, i can replace the long version with the short version. Tia. REed

...(ImmBranch &Br) { > MachineInstr *MI = Br.MI; > MachineBasicBlock *MBB = MI->getParent(); > if (!isThumb1) > llvm_unreachable("fixupUnconditionalBr is Thumb1 only!"); > > // Use BL to implement far jump. > Br.MaxDisp = (1 << 21) * 2; > MI->setDesc(TII->get(ARM::tBfar)); > BBInfo[MBB->getNumber()].Size += 2; > adjustBBOffsetsAfter(MBB); > HasFarJump = true; > ++NumUBrFixed; > > DEBUG(dbgs() << " Changed B to long jump " << *MI); > > return true; > } > > ___________________...

...neInstr *MI = Br.MI; >> MachineBasicBlock *MBB = MI->getParent(); >> if (!isThumb1) >> llvm_unreachable("fixupUnconditionalBr is Thumb1 only!"); >> >> // Use BL to implement far jump. >> Br.MaxDisp = (1 << 21) * 2; >> MI->setDesc(TII->get(ARM::tBfar)); >> BBInfo[MBB->getNumber()].Size += 2; >> adjustBBOffsetsAfter(MBB); >> HasFarJump = true; >> ++NumUBrFixed; >> >> DEBUG(dbgs() << " Changed B to long jump " << *MI); >> >> return true; &...

Looking through the X86 GlobalISEL code for selecting loads and stores, I'm not seeing the creation of the MachineMemOperands I'd expect to see and do see being generated by SelectionDAG.  Is this simply an oversight, or is there some aspect of the new design which pushes us away from MMOs? Various parts of the machine instruction level optimization passes use the existence and

...continue; - // ARMv4T requires BX, see emitEpilogue - if (STI.hasV4TOps() && !STI.hasV5TOps()) + + // ARMv4T and tail call returns require BX, see emitEpilogue + if ((STI.hasV4TOps() && !STI.hasV5TOps())) continue; + Reg = ARM::PC; (*MIB).setDesc(TII.get(ARM::tPOP_RET)); MIB.copyImplicitOps(&*MI); Index: ARMSubtarget.cpp =================================================================== --- ARMSubtarget.cpp (Revision 225589) +++ ARMSubtarget.cpp (Arbeitskopie) @@ -262,7 +262,7 @@ SupportsTailCall = !isTargetIOS() || !getTar...

...nInstrInfo *QII = (const HexagonInstrInfo *) TII; >> + >> + int NewOpcode; >> + if (RC == Hexagon::PredRegsRegisterClass) >> + NewOpcode = GetDotNewPredOp(MI->getOpcode()); >> + else >> + NewOpcode = GetDotNewOp(MI->getOpcode()); >> + MI->setDesc(QII->get(NewOpcode)); >> + >> + return true; >> +} >> + >> +// Returns the most basic instruction for the .new predicated instructions and >> +// new-value stores. >> +// For example, all of the following instructions will be converted back to the >&...