search for: getdesc

With a modified copy of LLVM (so it's probably my fault) I'm getting an assertion failure because isTwoAddrUse (in TwoAddressInstructionPass.cpp) is being called with a MachineInstr MI such that MI.getNumOperands() is 2, but MI.getDesc().getNumOperands() is 5. The assertion fails when that function calls MI.getOperand(2). My question is: is isTwoAddrUse doing the right thing here? static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { const TargetInstrDesc &TID = MI.getDesc(); unsigned NumO...

...t MkRules.dist MkRules.rules > MkRules -------- Building ../../../library/base/R/Rprofile from ../../library/profile/Common.R ../../library/profile/Rprofile.windows-------- mkdir -p ../../../library/base/R cp -p html/rwin.html ../../../doc/html/index.html make[3]: *** No rule to make target `etc/GETDESC', needed by `fixetc'. Stop. make[2]: *** [fixfiles] Error 2 make[1]: *** [rbuild] Error 2 make: *** [all] Error 2 Any help? Thanks, Jo

I see strangeness on Thumb TST (tTST) predicate 'isCompare' It is true for regular ARM, false for Thumb: (gdb) p MI->dump() TSTri %reg16397, 3, pred:14, pred:%reg0, %CPSR<imp-def>; GPR:% reg16397 $24 = void (gdb) p MI->getDesc().isCompare() $25 = true (gdb) p MI->dump() tTST %reg16396, %reg16397, pred:14, pred:%reg0, %CPSR<imp-def>; tGPR:%reg16396,16397 $22 = void (gdb) p MI->getDesc().isCompare() $23 = false Is this intentional or just an oversight? In latter case how do I fix it? Tablegen input?...

...errides this, and provides this more-customized definition: bool ARMBaseInstrInfo:: hasLowDefLatency(const InstrItineraryData *ItinData, const MachineInstr *DefMI, unsigned DefIdx) const { if (!ItinData || ItinData->isEmpty()) return false; unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask; if (DDomain == ARMII::DomainGeneral) { unsigned DefClass = DefMI->getDesc().getSchedClass(); int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx); return (DefCycle != -1 && DefCycle <= 2); } return false; } So it won't...

...if wrote: > I see strangeness on Thumb TST (tTST) predicate 'isCompare' > > It is true for regular ARM, false for Thumb: > > (gdb) p MI->dump() > TSTri %reg16397, 3, pred:14, pred:%reg0, %CPSR<imp-def>; GPR:% > reg16397 > $24 = void > (gdb) p MI->getDesc().isCompare() > $25 = true > > > (gdb) p MI->dump() > tTST %reg16396, %reg16397, pred:14, pred:%reg0, %CPSR<imp-def>; > tGPR:%reg16396,16397 > $22 = void > (gdb) p MI->getDesc().isCompare() > $23 = false > > > Is this intentional or just an ov...

...block label and the assembly becomes invalid. I fixed this in the MBlaze backend by overriding AsmPrinter::isBlockOnlyReachableByFallthrough and replaced (at the end of the function): // Otherwise, check the last instruction. const MachineInstr &LastInst = Pred->back(); return !LastInst.getDesc().isBarrier(); with: // Check if the last terminator is an unconditional branch. MachineBasicBlock::const_iterator I = Pred->end(); while (I != Pred->begin() && !(--I)->getDesc().isTerminator()) ; // Noop return I == Pred->end() || !I->getDesc().isBarrier(); Notice,...

The Sparc, Microblaze, and Mips code generators implement branch delay slots. They all seem to exhibit the same bug, which is not surprising since the code is very similar. If I compile code with this snippit: while (n--) *s++ = (char) c; I get this (for the Microblaze): swi r19, r1, 0 add r3, r0, r0 cmp r3, r3, r7 beqid r3,

...ge collection.")); Collector = GC->instantiate(); // nowhere for (CollectorRegistry::iterator I = CollectorRegistry::begin(), E = CollectorRegistry::end(); I ! = E; ++I) cout << I->getName() << ": " << I->getDesc() << "\n"; Granted, my needs are currently simple. The default entry type has just the name, description, and use the default constructor. To convert, many registries in the system would need to also define: 1. An custom entry type, particularly where the default constructor...

Hi, I notice that the following recent addition X86::CondCode X86::getCondFromBranch(const MachineInstr &MI) { switch (MI.getOpcode()) { default: return X86::COND_INVALID; case X86::JCC_1: return static_cast<X86::CondCode>( MI.getOperand(MI.getDesc().getNumOperands() - 1).getImm()); } } returns an invalid condition for JCC_2 and JCC_4 conditional opcodes. What is the suggested way to figure out the condition code for JCC_2 and JCC_4? Should I just roll one up for myself to handle such opcodes based on the above? Am I missing something co...

On Sep 17, 2009, at 6:03 PM, Duncan Sands wrote: > Hi Bill, > >>>> Yeah. The logic will need tweaking for sure. I'm also concerned >>>> about the >>>> _Unwind_resume() call. GCC emits a call site region for it in the >>>> exception >>>> table. We...kind of do that. It looks like it's being included in >>>>

...MachineFunction &MF) { for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end(); BBI != BBE; ++BBI) { for (MachineBasicBlock::iterator MI = BBI->begin(), ME = BBI->end(); MI != ME; ++MI) { if (MI->getDesc().isCall()) { /// Standard code need for adding a post call safe point; } else if (MI->getDebucLoc().getCol() == 1) { /// Standard code need for adding a post call safe point; } } } So it really looks like what we already have, except this special tric...

...: > What function provides the encoding length? X86 in particular is so > difficult to encode that only the old style JIT and the MC Code > Emitter could possibly know how many bytes something takes. The getSize() method of MCInstrDesc which can be fetched from a MachineInstr using the getDesc() method: http://llvm.org/doxygen/classllvm_1_1MCInstrDesc.html#ae8a17b854d9787d11797d9334a22647d Does this method not work as advertised in Doxygen? -- John T. > > On Tue, Oct 23, 2012 at 11:58 AM, John Criswell <criswell at illinois.edu > <mailto:criswell at illinois.edu>&g...

On Tue, Nov 17, 2015 at 11:15 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 11/17/2015 12:26 PM, Rail Shafigulin wrote: > >> >> I tried setting >> let mayLoad = 1 { >> class InstrLD .... { >> } >> } >> >> But that didn't seem to work. When I looked at the debug output the >> latency for the load

...{ > for (MachineFunction::iterator BBI = MF.begin(), > BBE = MF.end(); BBI != BBE; ++BBI) { > for (MachineBasicBlock::iterator MI = BBI->begin(), > ME = BBI->end(); MI != ME; ++MI) { > if (MI->getDesc().isCall()) { > /// Standard code need for adding a post call safe point; > } else if (MI->getDebucLoc().getCol() == 1) { > /// Standard code need for adding a post call safe point; > } > } > } > > So it really looks like what w...

...ctions that can be folded with the user of the register by changing the user to an immediate instruction. And it wouldn't be set on an instruction like "addl $0, %eax" or "addl $0, (%ecx)" either since those aren't moves. For X86 you can try using "X86II::hasImm(MI.getDesc().TSFlags)" that's what the encoder uses to determine if there's an immediate to encode at the end of the instruction encoding. ~Craig On Fri, Feb 9, 2018 at 1:13 PM, S. Bharadwaj Yadavalli <bharadwajy at gmail.com > wrote: > I am trying to categorize the machine instruc...

...was able to understand the Codegen infrastructure, ARMInstrInfo.td file has complete description of the instructions which modify the status flags. For example, we have description for both ADD and ADDS. But the problem is that in LLVM, we have a single "ADD" Instruction. Thus when we do getDesc(add), we get the descripiton corresponding to "ADD". When I was reading the code, I got a feeling that if we are able to modify this selection of "ADD" to "ADDS"( provided we somehow determine that we need ADDS here), then everything else related to ARM instruction gen...

I am trying to categorize the machine instructions based on associated static (i.e., as encoded in .td file) machine description and the corresponding APIs. I would like to perform appropriate actions based on the kind of instruction in a tool that I am working on. For example, I'd like to distinguish between memop instructions involving immediate vs register. While it appears that I would be

...ions have implicit register operands. If you are not including these in your calculations you will probably have some errors. My apologies for not mentioning this earlier. You can find the set of implicit uses and defs by querying the TargetInstDesc object for each MachineInstr (call MachineInstr::getDesc() to get it, and then the TargetInstrDesc::getImplicitUses() and TargetInstrDesc::getImplicitDefs() methods to find the regs used/definied by this instr). 2) How are you making sure that interfering virtregs never receive the same physreg? If you're using the LiveIntervals analysis (and the Li...

Hal, that’s a good point. There are more manually-maintained tables in the X86 backend that should probably be tablegened: the memory-folding tables and ReplaceableInstrs, to name a couple. If you have ideas on how to get these auto-generated, please let us know. From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of Hal Finkel via llvm-dev Sent: Wednesday, November 23, 2016

...Codegen infrastructure, > ARMInstrInfo.td file has complete description of the instructions > which modify the status flags. For example, we have description for > both ADD and ADDS. But the problem is that in LLVM, we have a single > "ADD" Instruction. Thus when we do getDesc(add), we get the > descripiton corresponding to "ADD". When I was reading the code, I > got a feeling that if we are able to modify this selection of "ADD" > to "ADDS"( provided we somehow determine that we need ADDS here), > then everything else re...