Displaying 7 results from an estimated 7 matches for "set_cr3".
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set_cr4
2020 Feb 07
0
[RFC PATCH v7 11/78] KVM: x86: add .control_cr3_intercept() to struct kvm_x86_ops
...level)
#define KVM_NR_FIXED_MTRR_REGION 88
#define KVM_NR_VAR_MTRR 8
+#define CR_TYPE_R 1
+#define CR_TYPE_W 2
+#define CR_TYPE_RW 3
+
#define ASYNC_PF_PER_VCPU 64
enum kvm_reg {
@@ -1064,6 +1068,8 @@ struct kvm_x86_ops {
void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0);
void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3);
int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4);
+ void (*control_cr3_intercept)(struct kvm_vcpu *vcpu, int type,
+ bool enable);
void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer);
void (*get_idt)(struct kvm_vcpu *vcpu, struct desc...
2020 Feb 07
0
[RFC PATCH v7 12/78] KVM: x86: add .cr3_write_intercepted()
...kvm_vcpu *vcpu)
+{
+ struct vcpu_svm *svm = to_svm(vcpu);
+
+ return is_cr_intercept(svm, INTERCEPT_CR3_WRITE);
+}
+
static void svm_control_cr3_intercept(struct kvm_vcpu *vcpu, int type,
bool enable)
{
@@ -7311,6 +7318,7 @@ static struct kvm_x86_ops svm_x86_ops __ro_after_init = {
.set_cr3 = svm_set_cr3,
.set_cr4 = svm_set_cr4,
.control_cr3_intercept = svm_control_cr3_intercept,
+ .cr3_write_intercepted = svm_cr3_write_intercepted,
.set_efer = svm_set_efer,
.get_idt = svm_get_idt,
.set_idt = svm_set_idt,
diff --git a/arch/x86/kvm/vmx/vmx.c b/arch/x86/kvm/vmx/vmx.c
index 4b6...
2007 Apr 18
0
[RFC/PATCH PV_OPS X86_64 08/17] paravirt_ops - memory managment
...===============
--- clean-start.orig/include/asm-x86_64/tlbflush.h
+++ clean-start/include/asm-x86_64/tlbflush.h
@@ -4,6 +4,7 @@
#include <linux/mm.h>
#include <asm/processor.h>
+
static inline unsigned long get_cr3(void)
{
unsigned long cr3;
@@ -16,7 +17,7 @@ static inline void set_cr3(unsigned long
asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory");
}
-static inline void __flush_tlb(void)
+static inline void __native_flush_tlb(void)
{
set_cr3(get_cr3());
}
@@ -33,17 +34,24 @@ static inline void set_cr4(unsigned long
asm volatile("m...
2007 Apr 18
0
[RFC/PATCH PV_OPS X86_64 08/17] paravirt_ops - memory managment
...===============
--- clean-start.orig/include/asm-x86_64/tlbflush.h
+++ clean-start/include/asm-x86_64/tlbflush.h
@@ -4,6 +4,7 @@
#include <linux/mm.h>
#include <asm/processor.h>
+
static inline unsigned long get_cr3(void)
{
unsigned long cr3;
@@ -16,7 +17,7 @@ static inline void set_cr3(unsigned long
asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory");
}
-static inline void __flush_tlb(void)
+static inline void __native_flush_tlb(void)
{
set_cr3(get_cr3());
}
@@ -33,17 +34,24 @@ static inline void set_cr4(unsigned long
asm volatile("m...
2007 Apr 18
2
[PATCH] x86_64 paravirt_ops port
...=
--- linux-2.6.19-quilt.orig/include/asm-x86_64/tlbflush.h
+++ linux-2.6.19-quilt/include/asm-x86_64/tlbflush.h
@@ -4,6 +4,7 @@
#include <linux/mm.h>
#include <asm/processor.h>
+
static inline unsigned long get_cr3(void)
{
unsigned long cr3;
@@ -16,7 +17,7 @@ static inline void set_cr3(unsigned long
asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory");
}
-static inline void __flush_tlb(void)
+static inline void __native_flush_tlb(void)
{
set_cr3(get_cr3());
}
@@ -33,17 +34,24 @@ static inline void set_cr4(unsigned long
asm volatile("m...
2007 Apr 18
2
[PATCH] x86_64 paravirt_ops port
...=
--- linux-2.6.19-quilt.orig/include/asm-x86_64/tlbflush.h
+++ linux-2.6.19-quilt/include/asm-x86_64/tlbflush.h
@@ -4,6 +4,7 @@
#include <linux/mm.h>
#include <asm/processor.h>
+
static inline unsigned long get_cr3(void)
{
unsigned long cr3;
@@ -16,7 +17,7 @@ static inline void set_cr3(unsigned long
asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory");
}
-static inline void __flush_tlb(void)
+static inline void __native_flush_tlb(void)
{
set_cr3(get_cr3());
}
@@ -33,17 +34,24 @@ static inline void set_cr4(unsigned long
asm volatile("m...
2020 Feb 07
78
[RFC PATCH v7 00/78] VM introspection
The KVM introspection subsystem provides a facility for applications
running on the host or in a separate VM, to control the execution of
other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs,
MSRs etc.), alter the page access bits in the shadow page tables (only
for the hardware backed ones, eg. Intel's EPT) and receive notifications
when events of interest have taken place