search for: set_cr4

...| 8 ++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 9032c996ebdb..d2fe08f44084 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1070,6 +1070,7 @@ struct kvm_x86_ops { int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); void (*control_cr3_intercept)(struct kvm_vcpu *vcpu, int type, bool enable); + bool (*cr3_write_intercepted)(struct kvm_vcpu *vcpu); void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr...

...| 8 ++++++++ 3 files changed, 17 insertions(+) diff --git a/arch/x86/include/asm/kvm_host.h b/arch/x86/include/asm/kvm_host.h index 89c0bd6529a5..ac45aacc9fc0 100644 --- a/arch/x86/include/asm/kvm_host.h +++ b/arch/x86/include/asm/kvm_host.h @@ -1117,6 +1117,7 @@ struct kvm_x86_ops { int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); void (*control_cr3_intercept)(struct kvm_vcpu *vcpu, int type, bool enable); + bool (*cr3_write_intercepted)(struct kvm_vcpu *vcpu); void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr...

...VAR_MTRR 8 +#define CR_TYPE_R 1 +#define CR_TYPE_W 2 +#define CR_TYPE_RW 3 + #define ASYNC_PF_PER_VCPU 64 enum kvm_reg { @@ -1064,6 +1068,8 @@ struct kvm_x86_ops { void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); void (*set_cr3)(struct kvm_vcpu *vcpu, unsigned long cr3); int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); + void (*control_cr3_intercept)(struct kvm_vcpu *vcpu, int type, + bool enable); void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); void (*set_idt)(struct kvm_vcpu *vcpu, struct d...

...R 8 +#define CR_TYPE_R 1 +#define CR_TYPE_W 2 +#define CR_TYPE_RW 3 + #define ASYNC_PF_PER_VCPU 64 enum kvm_reg { @@ -1111,6 +1115,8 @@ struct kvm_x86_ops { void (*get_cs_db_l_bits)(struct kvm_vcpu *vcpu, int *db, int *l); void (*set_cr0)(struct kvm_vcpu *vcpu, unsigned long cr0); int (*set_cr4)(struct kvm_vcpu *vcpu, unsigned long cr4); + void (*control_cr3_intercept)(struct kvm_vcpu *vcpu, int type, + bool enable); void (*set_efer)(struct kvm_vcpu *vcpu, u64 efer); void (*get_idt)(struct kvm_vcpu *vcpu, struct desc_ptr *dt); void (*set_idt)(struct kvm_vcpu *vcpu, struct d...

...@@ -16,7 +17,7 @@ static inline void set_cr3(unsigned long asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory"); } -static inline void __flush_tlb(void) +static inline void __native_flush_tlb(void) { set_cr3(get_cr3()); } @@ -33,17 +34,24 @@ static inline void set_cr4(unsigned long asm volatile("mov %0,%%cr4" :: "r" (cr4) : "memory"); } -static inline void __flush_tlb_all(void) +static inline void __native_flush_tlb_all(void) { unsigned long cr4 = get_cr4(); set_cr4(cr4 & ~X86_CR4_PGE); /* clear PGE */ set_cr4(cr4);...

...@@ -16,7 +17,7 @@ static inline void set_cr3(unsigned long asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory"); } -static inline void __flush_tlb(void) +static inline void __native_flush_tlb(void) { set_cr3(get_cr3()); } @@ -33,17 +34,24 @@ static inline void set_cr4(unsigned long asm volatile("mov %0,%%cr4" :: "r" (cr4) : "memory"); } -static inline void __flush_tlb_all(void) +static inline void __native_flush_tlb_all(void) { unsigned long cr4 = get_cr4(); set_cr4(cr4 & ~X86_CR4_PGE); /* clear PGE */ set_cr4(cr4);...

...pu *vcpu, unsigned long cr0) if (!(cr0 & X86_CR0_PG) && kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE)) return 1; + if (!kvmi_cr_event(vcpu, 0, old_cr0, &cr0)) + return 1; + kvm_x86_ops->set_cr0(vcpu, cr0); if ((cr0 ^ old_cr0) & X86_CR0_PG) { @@ -935,6 +938,9 @@ int kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4) return 1; } + if (!kvmi_cr_event(vcpu, 4, old_cr4, &cr4)) + return 1; + if (kvm_x86_ops->set_cr4(vcpu, cr4)) return 1; @@ -951,6 +957,7 @@ EXPORT_SYMBOL_GPL(kvm_set_cr4); int kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3) {...

...gt; 32; + + asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ + : : "a" (eax), "d" (edx), "c" (index)); +} + +static void guest_xsetbv_test(void) +{ + const int SSE_BIT = 1 << 1; + const int AVX_BIT = 1 << 2; + u64 xcr0; + + /* avoid #UD */ + set_cr4(get_cr4() | X86_CR4_OSXSAVE); + + xcr0 = xgetbv(0); + if (xcr0 & AVX_BIT) + xcr0 &= ~AVX_BIT; + else + xcr0 |= (AVX_BIT | SSE_BIT); + + xsetbv(0, xcr0); +} + static void guest_code(void) { while (true) { @@ -99,6 +141,9 @@ static void guest_code(void) case GUEST_TEST_HYPERCALL:...

...gt; 32; + + asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */ + : : "a" (eax), "d" (edx), "c" (index)); +} + +static void guest_xsetbv_test(void) +{ + const int SSE_BIT = 1 << 1; + const int AVX_BIT = 1 << 2; + u64 xcr0; + + /* avoid #UD */ + set_cr4(get_cr4() | X86_CR4_OSXSAVE); + + xcr0 = xgetbv(0); + if (xcr0 & AVX_BIT) + xcr0 &= ~AVX_BIT; + else + xcr0 |= (AVX_BIT | SSE_BIT); + + xsetbv(0, xcr0); +} + static void guest_code(void) { while (true) { @@ -104,6 +146,9 @@ static void guest_code(void) case GUEST_TEST_HYPERCALL:...

...@@ -16,7 +17,7 @@ static inline void set_cr3(unsigned long asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory"); } -static inline void __flush_tlb(void) +static inline void __native_flush_tlb(void) { set_cr3(get_cr3()); } @@ -33,17 +34,24 @@ static inline void set_cr4(unsigned long asm volatile("mov %0,%%cr4" :: "r" (cr4) : "memory"); } -static inline void __flush_tlb_all(void) +static inline void __native_flush_tlb_all(void) { unsigned long cr4 = get_cr4(); set_cr4(cr4 & ~X86_CR4_PGE); /* clear PGE */ set_cr4(cr4);...

...@@ -16,7 +17,7 @@ static inline void set_cr3(unsigned long asm volatile("mov %0,%%cr3" :: "r" (cr3) : "memory"); } -static inline void __flush_tlb(void) +static inline void __native_flush_tlb(void) { set_cr3(get_cr3()); } @@ -33,17 +34,24 @@ static inline void set_cr4(unsigned long asm volatile("mov %0,%%cr4" :: "r" (cr4) : "memory"); } -static inline void __flush_tlb_all(void) +static inline void __native_flush_tlb_all(void) { unsigned long cr4 = get_cr4(); set_cr4(cr4 & ~X86_CR4_PGE); /* clear PGE */ set_cr4(cr4);...

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VMs (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VM-s (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place

The KVM introspection subsystem provides a facility for applications running on the host or in a separate VM, to control the execution of other VM-s (pause, resume, shutdown), query the state of the vCPUs (GPRs, MSRs etc.), alter the page access bits in the shadow page tables (only for the hardware backed ones, eg. Intel's EPT) and receive notifications when events of interest have taken place