search for: selectaddrshlimm

Displaying 4 results from an estimated 4 matches for "selectaddrshlimm".

2016 Sep 28
2
Incompatible type assertion from llvm-tblgen
...D=4] And map it to a load.idx instruction with the following semantics: load.idx r1,r2,r3,SIZE r1 <- mem[r2 + (r3 << sizeof(operand))] That somehow the pattern matching dag fragment would need to be something like I had in ADDR_SHLI definition: def ADDR_SHLI : Addr< 2, "SelectAddrShlImm", (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >; Now If I have to create a subclass of Operand and define it's EncoderMethod in C++, does that mean the pattern matching (matching the shift left and add) now happens on the C++ side as well? Phil > -Kr...
2016 Oct 04
2
Incompatible type assertion from llvm-tblgen
...with the following semantics: >> load.idx r1,r2,r3,SIZE r1 <- mem[r2 + (r3 << sizeof(operand))] >> >> That somehow the pattern matching dag fragment would need to be >> something like I had in ADDR_SHLI definition: >> def ADDR_SHLI : Addr< 2, "SelectAddrShlImm", >> (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >; >> >> >> Now If I have to create a subclass of Operand and define it's >> EncoderMethod in C++, does that mean the pattern matching (matching the >> shift left and add) no...
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
...MemOperand" in { def ADDR_RR : Addr< 2, "SelectAddrRegReg", (ops GPRC:$base, GPRC:$offsetreg) >; def ADDR_RI : Addr< 2, "SelectAddrRegImm", (ops GPRC:$base, i64imm:$offsetimm) >; def ADDR_SHLI : Addr< 2, "SelectAddrShlImm", (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >; } If I change the LoadOpIdx definition to: class LoadOpIdx< bits<7> op, string instr_asm, OperandInfo info, InstrItinClass itin=II_LOAD1_RR >...
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
...I need to create some other intermediate node type for a shifted address? Phil On Mon, Sep 26, 2016 at 1:42 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 9/26/2016 3:36 PM, Phil Tomson via llvm-dev wrote: > >> def ADDR_SHLI : Addr< 2, "SelectAddrShlImm", >> (ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >; >> > > You have a dag in the list of operands. That won't work. > > -Krzysztof > > -- > Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted > by The...