Displaying 8 results from an estimated 8 matches for "selectaddrregimm".
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
But don't the defs for ADDR_RR and ADDR_RI also contain dags?
def ADDR_RR : Addr< 2, "SelectAddrRegReg",
(ops GPRC:$base, GPRC:$offsetreg) >;
def ADDR_RI : Addr< 2, "SelectAddrRegImm",
(ops GPRC:$base, i64imm:$offsetimm) >;
Do I need to create some other intermediate node type for a shifted address?
Phil
On Mon, Sep 26, 2016 at 1:42 PM, Krzysztof Parzyszek via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> On 9/26/2016 3:36 PM, Phil T...
2016 Sep 26
2
Incompatible type assertion from llvm-tblgen
...; i64, numArgs, funcName, [], [SDNPWantParent] > {
let MIOperandInfo = opInfo;
}
let PrintMethod = "printMemOperand" in {
def ADDR_RR : Addr< 2, "SelectAddrRegReg",
(ops GPRC:$base, GPRC:$offsetreg) >;
def ADDR_RI : Addr< 2, "SelectAddrRegImm",
(ops GPRC:$base, i64imm:$offsetimm) >;
def ADDR_SHLI : Addr< 2, "SelectAddrShlImm",
(ops GPRC:$base, ( shl GPRC:$offsetreg, (i64 3))) >;
}
If I change the LoadOpIdx definition to:
class LoadOpIdx< bits<7> op,...
2010 Jan 30
3
[LLVMdev] [patch] MicroBlaze Backend
...ic allocas normally ends with
stack register adjustment, you don't need anything special here.
>+bool MBlazeTargetLowering::
>+SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) {
Move this to ISelDAGToDAG file
>+bool MBlazeTargetLowering::
>+SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) {
Likewise
>+def : Proc<"v400", []>;
>+def : Proc<"v500", []>;
>+def : Proc<"v600", []>;
>+def : Proc<"v700", []>;
>+def : Proc<"v710"...
2010 Jan 30
0
[LLVMdev] [patch] MicroBlaze Backend
On Jan 29, 2010, at 9:42 AM, Wesley Peck wrote:
> I have been working on a LLVM backend for the MicroBlaze soft-processor:
> http://www.xilinx.com/tools/microblaze.htm
> http://en.wikipedia.org/wiki/MicroBlaze
Very Cool!
> Attached is the initial MicroBlaze patch. It does the following:
> 1. Adds mblaze as a target in configure and configure.ac
> 2. Adds mblaze specific
2010 Jan 30
0
[LLVMdev] [patch] MicroBlaze Backend
...ckend. I will take a look at removing this for the next patch.
>
>> +bool MBlazeTargetLowering::
>> +SelectAddrRegReg(SDValue N, SDValue &Base, SDValue &Index, SelectionDAG &DAG) {
> Move this to ISelDAGToDAG file
>
>> +bool MBlazeTargetLowering::
>> +SelectAddrRegImm(SDValue N, SDValue &Disp, SDValue &Base, SelectionDAG &DAG) {
> Likewise
Done.
>
>> +def : Proc<"v400", []>;
>> +def : Proc<"v500", []>;
>> +def : Proc<"v600", []>;
>> +def : Proc<"v700", []>...
2010 Jan 29
3
[LLVMdev] [patch] MicroBlaze Backend
I have been working on a LLVM backend for the MicroBlaze soft-processor:
http://www.xilinx.com/tools/microblaze.htm
http://en.wikipedia.org/wiki/MicroBlaze
Attached is the initial MicroBlaze patch. It does the following:
1. Adds mblaze as a target in configure and configure.ac
2. Adds mblaze specific intrinsics in include/llvm/IntrinsicsMBlaze.td and include/llvm/Intrinsics.td
3. Adds mblaze
2016 Sep 28
2
Incompatible type assertion from llvm-tblgen
...6 3:58 PM, Phil Tomson wrote:
>
>> But don't the defs for ADDR_RR and ADDR_RI also contain dags?
>>
>> def ADDR_RR : Addr< 2, "SelectAddrRegReg",
>> (ops GPRC:$base, GPRC:$offsetreg) >;
>> def ADDR_RI : Addr< 2, "SelectAddrRegImm",
>> (ops GPRC:$base, i64imm:$offsetimm) >;
>>
>> Do I need to create some other intermediate node type for a shifted
>> address?
>>
>
> Technically yes, but the list of allowed types is limited. "RegisterClass"
> (e.g G...
2016 Oct 04
2
Incompatible type assertion from llvm-tblgen
On Wed, Sep 28, 2016 at 12:54 PM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 9/28/2016 2:44 PM, Phil Tomson wrote:
>
>> And map it to a load.idx instruction with the following semantics:
>> load.idx r1,r2,r3,SIZE r1 <- mem[r2 + (r3 << sizeof(operand))]
>>
>> That somehow the pattern matching dag fragment would need to be