search for: sdtcisvt

...Reg 0x15c9bb988, Register:i32 %I18, 0x15c9bb578 0x15c9bb9f0: i32 = Register %I18 0x15c9bb578: i32,ch,glue = CopyFromReg 0x15c967b38, Register:i32 %vreg0 0x15c9bb510: i32 = Register %vreg0 My TD for this has: def SDT_MYCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; def SDT_MYCallSeqEnd : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; def MYCallseqStart : SDNode<"ISD::CALLSEQ_START", SDT_MYCallSeqStart, [SDNPHasChain, SDNPOutGlue]>;...

...15c9bb578 > 0x15c9bb9f0: i32 = Register %I18 > 0x15c9bb578: i32,ch,glue = CopyFromReg 0x15c967b38, > Register:i32 %vreg0 > 0x15c9bb510: i32 = Register %vreg0 > > My TD for this has: > > def SDT_MYCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, > i32>]>; > def SDT_MYCallSeqEnd : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, > i32>]>; > def MYCallseqStart : SDNode<"ISD::CALLSEQ_START", SDT_MYCallSeqStart, > [SDNPHas...

...r as I can tell, my implementation is pretty much identical to all of the in-tree targets, but I’m missing something and can’t see what it is. I have simplified my TD description to just: def MyCallseqStart : SDNode<"ISD::CALLSEQ_START", SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>, [SDNPHasChain, SDNPOutGlue]>; def MyCallseqEnd : SDNode<"ISD::CALLSEQ_END", SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>, [SDNPHasChain...

...U/SIInstrInfo.td > @@ -114,6 +114,15 @@ def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", > [SDNPMayStore, SDNPMemOperand, SDNPHasChain] > >; > > +def SIcmp_swap : SDNode<"AMDGPUISD::CMP_SWAP", > + SDTypeProfile<1, 2, > + [SDTCisVT<0, v2i32>, // return value (should be i32) > + SDTCisVT<1, i64>, // address > + SDTCisVT<2, v2i32> // src followed by cmp > + ]>, > + [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain] > +>; > + > def SIload_input : SDNode<&qu...

Hi Tom, Matt, I'm working on a project that needs few coherent atomic operations (HSA mode: load, store, compare-and-swap) for std::atomic_uint in HCC. the attached patch implements atomic compare and swap for SI+ (untested). I tried to stay within what was available, but there are few issues that I was unsure how to address: 1.) it currently uses v2i32 for both input and output. This

I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr. But I need to use an even/odd register pair to save its 2 operands. I define in mytarget.td: myfmdrr: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,     SDTCisSameAs<1, 2>]>; def my_fmdrr : ........... def myFMDRR : ....                       (outs FPR: $result), ins(GPR: $op1, GPR:$op2 )                        [(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )] I create myfmdrr instructure in...

...structions. If the instruction has a return value I am able to correctly match it, but if I try to create some tablegen code that has no return value, the instruction gets deleted. Here is my profile/node/pattern. Profile: def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [ SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32> ]>; Node: def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>; Pattern: def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD, "_id($id)", atom_g_add_noret>; I am Loweri...

...om Hexagon the following, adapting it to my registers: - In ISelLowering.h: CONST32 and CONST32_GP - In ISelLowering.cpp: LowerGlobalAddress - In TargetObjectFile.cpp: isGlobalInSmallSection - In InstrInfo.td: def SDTmyCONST32 : SDTypeProfile<1, 1, [ SDTCisVT<0, i32>, SDTCisVT<1, i32>, SDTCisPtrTy<0>]>; def myCONST32 : SDNode<"myISD::CONST32", SDTmyCONST32>; def myCONST32_GP : SDNode<"myISD::CONST32_GP", SDTmy...

...lass is easy enough to implement in the RegisterInfo.td file. The next thing I wanted to do is create a Pseudo-Element similar to the ExtractElementF64 in mips. I added the following Code to InstrFPU.td (and added the CopyF64 ISD to another file): def SDT_MipsCopyF64 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, SDTCisVT<1, f64>]>; def MipsCopyF64 : SDNode<"MIPSISD::CopyF64", SDT_MIPSCopyF64>; I also changed CPU64Regs to CPU64PRegs ( My 64 bit paired register class) in the DMFC1 rule f...

...ipermail/llvmdev/2006-October/006892.html but was wondering if anyone could comment on this process in a little more detail. I presume I need to define various target independent nodes, like below ... def SDT_SABREcondbr : SDTypeProfile<0,3, // no result, 3 operands, rega, regb, immediate [ SDTCisVT<1,i32>, SDTCisVT<2,OtherVT> ]>; def SABREcondbranch: SDNode <"SABREISD::COND_BRANCH" , SDT_SABREcondbr, [SDNPHasChain]>; def COND_BRANCH: Pseudo<(ops IntRegs:$a, IntRegs:$b, target:$dst), "${:comment}COND_BRANCH $a, $b, $dst...

...r an existing example, have a look at the memory barrier instruction definitions for the ARM target (DMB and DMB_MCR in ARMInstrInfo.td). Regards, Jim > > Here is my profile/node/pattern. > Profile: > def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [ > SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32> > ]>; > Node: > def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>; > > Pattern: > def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD, > "_id($id)",...

...'s. In other cases, they are copies. Evan On Feb 19, 2009, at 2:00 AM, 任坤 wrote: I define a pattern to move two 32bits gpr to 64bits fpr. like arm instructure fmdrr. But I need to use an even/odd register pair to save its 2 operands. I define in mytarget.td: myfmdrr: SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>,     SDTCisSameAs<1, 2>]>; def my_fmdrr : ........... def myFMDRR : ....                       (outs FPR: $result), ins(GPR: $op1, GPR:$op2 )                        [(setFPR: $result, (my_fmdrr GPR: $op1, GPR:$op2) )] I create myfmdrr instructure in...

...0x8502eb8, 0x8502f40 I probably have other issues, but solving this should help me solve other issues. Thanks again, Micah > > > > > Here is my profile/node/pattern. > > Profile: > > def SDTIL_BinAtomNoRet : SDTypeProfile<0, 3, [ > > SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32> > > ]>; > > Node: > > def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", > SDTIL_BinAtomNoRet, [SDNPHasChain]>; > > > > Pattern: > > def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,...

...[SDTCisSameAs<0, 1>]>; > > > I think for setting an implicit register, you still need to have 1 result > here. > > If you look at SDTX86CmpPTest, I think this is similar to what you are > trying to do. > > -Matt > def SDTX86CmpPTest : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisVec<1>, SDTCisSameAs<2, 1>]>; This is confusing to me. This tells me that there is 1 result but and 2 operands. But then it says that operands 2 and 1 are of the same type, SDTCi...

...1, isBarrier = 1 in def TCRETURNdi8 :Pseudo< (outs), Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 52957) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -42,17 +42,23 @@ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; - -def SDT_PPClarx : SDTypeProfile<1, 2, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32> +def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [ + SDTCisInt<0>, SDTCi...

...in the > RegisterInfo.td file. > > The next thing I wanted to do is create a Pseudo-Element similar to the > ExtractElementF64 in mips. I added the following Code to InstrFPU.td (and > added the CopyF64 ISD to another file): > > def SDT_MipsCopyF64 : SDTypeProfile<1, 1, [SDTCisVT<0, i64>, > SDTCisVT<1, f64>]>; > > def MipsCopyF64 : SDNode<"MIPSISD::CopyF64", > SDT_MIPSCopyF64>; > > I also changed CPU64Regs to CPU64PRegs ( My 64 bit paired registe...

...2:00 AM, 任坤 wrote: > >> I define a pattern to move two 32bits gpr to 64bits fpr. like arm >> instructure fmdrr. >> But I need to use an even/odd register pair to save its 2 operands. >> I define in mytarget.td: >> >> myfmdrr: >> SDTypeProfile<1, 2, [SDTCisVT<0, f64>, SDTCisVT<1, i32>, >> SDTCisSameAs<1, 2>]>; >> def my_fmdrr : ........... >> def myFMDRR : .... >> (outs FPR: $result), ins(GPR: $op1, GPR:$op2 ) >> [(setFPR: $result, (my_fmdrr GPR: $op1, GP...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...1, isBarrier = 1 in def TCRETURNdi8 :Pseudo< (outs), Index: lib/Target/PowerPC/PPCInstrInfo.td =================================================================== --- lib/Target/PowerPC/PPCInstrInfo.td (revision 53464) +++ lib/Target/PowerPC/PPCInstrInfo.td (working copy) @@ -42,17 +42,23 @@ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT> ]>; - -def SDT_PPClarx : SDTypeProfile<1, 2, [ - SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32> +def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [ + SDTCisInt<0>, SDTCi...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36