Displaying 20 results from an estimated 28 matches for "sdtcisint".
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...======
--- lib/Target/PowerPC/PPCInstrInfo.td (revision 52957)
+++ lib/Target/PowerPC/PPCInstrInfo.td (working copy)
@@ -42,17 +42,23 @@
SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
-
-def SDT_PPClarx : SDTypeProfile<1, 2, [
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
+def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [
+ SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
]>;
-def SDT_PPCstcx : SDTypeProfile<0, 3, [
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
+def...
2008 Jul 08
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
PPCTargetLowering::EmitInstrWithCustomInserter has a reference
to the current MachineFunction for other purposes. Can you use
MachineFunction::getRegInfo instead?
Dan
On Jul 8, 2008, at 1:56 PM, Gary Benson wrote:
> Would it be acceptable to change MachineInstr::getRegInfo from private
> to public so I can use it from
> PPCTargetLowering::EmitInstrWithCustomInserter?
>
>
2008 Jul 11
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...======
--- lib/Target/PowerPC/PPCInstrInfo.td (revision 53464)
+++ lib/Target/PowerPC/PPCInstrInfo.td (working copy)
@@ -42,17 +42,23 @@
SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
-
-def SDT_PPClarx : SDTypeProfile<1, 2, [
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
+def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [
+ SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
]>;
-def SDT_PPCstcx : SDTypeProfile<0, 3, [
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
+def...
2008 Jul 11
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Hi Gary,
This does not patch cleanly for me (PPCISelLowering.cpp). Can you
prepare a updated patch?
Thanks,
Evan
On Jul 10, 2008, at 11:45 AM, Gary Benson wrote:
> Cool, that worked. New patch attached...
>
> Cheers,
> Gary
>
> Evan Cheng wrote:
>> Just cast both values to const TargetRegisterClass*.
>>
>> Evan
>>
>> On Jul 10, 2008, at 7:36
2008 Jul 10
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Just cast both values to const TargetRegisterClass*.
Evan
On Jul 10, 2008, at 7:36 AM, Gary Benson wrote:
> Evan Cheng wrote:
>> How about?
>>
>> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
>> &PPC:G8RCRegClass;
>> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
>
> I tried something like that yesterday:
>
> const
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Evan Cheng wrote:
> How about?
>
> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
> &PPC:G8RCRegClass;
> unsigned TmpReg = RegInfo.createVirtualRegister(RC);
I tried something like that yesterday:
const TargetRegisterClass *RC =
is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass;
but I kept getting this error no matter how I arranged it:
2008 Jun 30
0
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
You need to insert new basic blocks and update CFG to accomplish this.
There is a hackish way to do this right now. Add a pseudo instruction
to represent this operation and mark it usesCustomDAGSchedInserter.
This means the intrinsic is mapped to a single (pseudo) node. But it
is then expanded into instructions that can span multiple basic
blocks. See
2008 Jul 09
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...======
--- lib/Target/PowerPC/PPCInstrInfo.td (revision 52957)
+++ lib/Target/PowerPC/PPCInstrInfo.td (working copy)
@@ -42,17 +42,23 @@
SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
-
-def SDT_PPClarx : SDTypeProfile<1, 2, [
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
+def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [
+ SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
]>;
-def SDT_PPCstcx : SDTypeProfile<0, 3, [
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
+def...
2008 Jul 08
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Would it be acceptable to change MachineInstr::getRegInfo from private
to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter?
Cheers,
Gary
Evan Cheng wrote:
> Look for createVirtualRegister. These are examples in
> PPCISelLowering.cpp.
>
> Evan
> On Jul 8, 2008, at 8:24 AM, Gary Benson wrote:
>
> > Hi Evan,
> >
> > Evan Cheng wrote:
2008 Jun 30
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Chris Lattner wrote:
> On Jun 27, 2008, at 8:27 AM, Gary Benson wrote:
> > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm:
> > $label),
> > "cmpw $rA, $rB\n\tbne- La${label}_exit",
> > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm:
> > $label)]>;
> > }
> >
> > ...and
2016 Jan 13
2
Expanding a PseudoOp and accessing the DAG
I've got this PseudoOp defined:
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
let Constraints = "$dst = $addr" in { //, Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs GPRC:$dst),
(ins i64imm:$sp...
2008 Jul 02
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
...======
--- lib/Target/PowerPC/PPCInstrInfo.td (revision 52957)
+++ lib/Target/PowerPC/PPCInstrInfo.td (working copy)
@@ -42,17 +42,23 @@
SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
]>;
-
-def SDT_PPClarx : SDTypeProfile<1, 2, [
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
+def SDT_PPCatomic_load_add : SDTypeProfile<1, 2, [
+ SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisInt<2>
]>;
-def SDT_PPCstcx : SDTypeProfile<0, 3, [
- SDTCisInt<0>, SDTCisPtrTy<1>, SDTCisVT<2, i32>
+def...
2009 Nov 30
1
[LLVMdev] Description of SDTypeProfile
Hi,
A piece of code in a target description file:
def SDTIntBinOp : SDTypeProfile<1, 2, [ // add, and, or, xor, udiv, etc.
SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>
]>;
May I understand "SDTCisSameAs<0, 1>, SDTCisSameAs<0, 2>, SDTCisInt<0>" as
below?
(Z = X + Y, for example);
Z:0
X:1
Y:2
X has same type as Z
Y has same type as Z
Z is a integer
Thanks
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2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...pattern should have void
types
The definitions it's complaining about:
//===----------------------------------------------------------------------===//
// RELADDR
//===----------------------------------------------------------------------===//
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,
1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
let Uses= [GRP] in {
def RelAddr : XSTGPseudo< (outs),
(ins GPRC:$spoff, GPRC:$dst),...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...;
>>
>> That's better, but now I get:
>>
>> XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires
>> exactly 2 operands!
>>
>> Which makes some sense as XSTGRELADDR is defined as:
>> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>,
>> SDTCisSameAs<0, 1>]>;
>> def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
>>
>
> The problem is that the pattern that you use in the instruction definition
> cannot have any value. That is, the top node has to consume...
2016 Jan 07
2
TableGen error message: top-level forms in instruction pattern should have void types
...mething like
> [(set GPRC:$dst, (XSTGRELADDR GPRC:$spoff))]
>
>
That's better, but now I get:
XSTGInstrInfo.td:902:3: error: In RelAddr: XSTGRELADDR node requires
exactly 2 operands!
Which makes some sense as XSTGRELADDR is defined as:
def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0,
1>]>;
def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
Phil
-Krzysztof
>
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
> ____________________________...
2008 Dec 05
2
[LLVMdev] (tablegen) Machine instruction without result
...uspect my tablegen description of this instruction to be erroneous, so I paste it below with comments what I think I am doing:
//define an instruction profile with zero results,
//2 inputs which are of the same type (int)
def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
SDTCisSameAs<0, 1>, SDTCisInt<0>
]>;
//define a node using that profile with a OutFlag
//property (which is a way to modelise e.g. HW internal CC registers?)
def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp, [SDNPOutFlag]>;
//define the instruction
def MYcmp : InstMYArch<(outs), (ins IntReg...
2016 Jan 08
2
TableGen error message: top-level forms in instruction pattern should have void types
On 1/7/2016 5:54 PM, Phil Tomson wrote:
> I got it to compile by changing to:
> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>,
> SDTCisSameAs<0, 1>]>;
> def XSTGRELADDR : SDNode<"XSTGISD::RELADDR", SDT_RELADDR>;
>
> let Uses= [GRP] in {
> def RelAddr : XSTGPseudo< (outs GPRC:$dst),
> (ins GPRC:$spoff, GPRC:$add...
2018 Jul 10
2
Stuck with instruction in tablegen
2008 Dec 05
0
[LLVMdev] (tablegen) Machine instruction without result
...s instruction to
> be erroneous, so I paste it below with comments what I think I am
> doing:
>
> //define an instruction profile with zero results,
> //2 inputs which are of the same type (int)
> def NOResSDTIntBinOp : SDTypeProfile<0, 2, [
> SDTCisSameAs<0, 1>, SDTCisInt<0>
> ]>;
>
> //define a node using that profile with a OutFlag
> //property (which is a way to modelise e.g. HW internal CC registers?)
> def MYcmpicc : SDNode<"MYISD::CMPICC", NOResSDTIntBinOp,
> [SDNPOutFlag]>;
>
>
> //define the instruction
&...