Displaying 20 results from an estimated 159 matches for "sdoperands".
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2006 May 05
2
[LLVMdev] ExecutionEngine blew the stack ?
Segfault in EE->getPointerToFunction.
I think it's blown the stack, gdb reports a never ending backtrace (below).
I generate llvm assembly and parse/verify OK.
Attached is the assembly. It is the smallest example
generated that causes the segfault.
If this EE uses a recursive function (??), it seems an inherent limitation
in how big llvm functions can be.
Simon.
gdb backtrace:
#0
2006 Dec 19
3
[LLVMdev] alias-aware scheduling
Hello,
I did a little experiment modifying LLVM to be able to use alias-analysis
information in scheduling so that independent memory operations may be
reordered.
Attached is a patch which implements this. I copied some routines from
DAGCombiner.cpp for using SDOperands with alias queries; it should
probably be factored out somewhere so the code can be shared. I
reorganized SelectionDAGLowering::getLoadFrom a little, to make it
simpler to use in other contexts.
Also, the patch fixes a bug where SelectionDAG::getLoad and
SelectionDAG::getStore were being called wi...
2007 Sep 24
2
[LLVMdev] RFC: Tail call optimization X86
On 24 Sep 2007, at 09:18, Evan Cheng wrote:
> +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -info-
> output-file - | grep asm-printer | grep 9
> +; change preceeding line form ... | grep 8 to ..| grep 9 since
> +; with new fastcc has std call semantics causing a stack adjustment
> +; after the function call
>
> Not sure if I understand this. Can you illustrate
2006 Nov 15
2
[LLVMdev] LowerCALL (TargetLowering)
Hi,
I am trying to write a LowerCALL() function for my (custom) target ISA.
All I need to do is map a CALL instruction directly onto an SDNode that
takes an equal number of arguments (very much alike intrinsics, except
that these are custom to my target.) I do not need to implement any call
sequences, stack frames etc.
I get the following assertion failure:
llc: LegalizeDAG.cpp:834:
2006 May 05
0
[LLVMdev] ExecutionEngine blew the stack ?
(resending with smaller attachement)
Segfault in EE->getPointerToFunction.
I think it's blown the stack, gdb reports a never ending backtrace (below).
I generate llvm assembly and parse/verify OK.
Attached is the assembly. It is the smallest example
generated that causes the segfault.
If this EE uses a recursive function (??), it seems an inherent limitation
in how big llvm functions
2008 Apr 21
0
[LLVMdev] RFC: PowerPC tail call optimization patch
On Apr 16, 2008, at 10:07 AM, Arnold Schwaighofer wrote:
> Hello Dale,
>
> this is an updated version of the tail call optimization patch for
> powerpc. could you have a look at it?
>
> i added code to support ppc64 (untested, will try to get access to
> ppc64 on a friend's machine).
> incorporated evan's formatting suggestions. ;)
>
> will run another round
2008 Apr 22
2
[LLVMdev] RFC: PowerPC tail call optimization patch
On Tue, Apr 22, 2008 at 12:30 AM, Evan Cheng <evan.cheng at apple.com> wrote:
> More nitpicks:
> ...
> No need for else here. :-)
Done
> SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
>
> Just change last statement to
> int SPDiff = (int)...
Done
>
> +bool
> +PPCTargetLowering::IsEligibleForTailCallOptimization(SDOperand Call,
> +
2007 Sep 24
0
[LLVMdev] RFC: Tail call optimization X86
On Sep 24, 2007, at 2:25 AM, Arnold Schwaighofer wrote:
>
> On 24 Sep 2007, at 09:18, Evan Cheng wrote:
>> +; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse2 -stats -info-
>> output-file - | grep asm-printer | grep 9
>> +; change preceeding line form ... | grep 8 to ..| grep 9 since
>> +; with new fastcc has std call semantics causing a stack adjustment
>>
2006 Dec 20
1
[LLVMdev] alias-aware scheduling
...chain operands during the construction
of the DAG, while the DAGCombiner code works by cleaning up chain operands in
a separate pass. It looks like the end result is pretty similar.
> > Attached is a patch which implements this. I copied some routines from
> > DAGCombiner.cpp for using SDOperands with alias queries; it should
> > probably be factored out somewhere so the code can be shared. I
> > reorganized SelectionDAGLowering::getLoadFrom a little, to make it
> > simpler to use in other contexts.
> >
> > Also, the patch fixes a bug where SelectionDAG::getLoa...
2007 Sep 25
2
[LLVMdev] RFC: Tail call optimization X86
> > FastCC use to be caller pops arguments so there was no stack
> > adjustment after the
> > call to qux. Now FastCC has callee pops arguments on return semantics
> > so the
> > x86 backend inserts a stack adjustment after the call.
> >
> > _array:
> > subl $12, %esp
> > movss LCPI1_0, %xmm0
> > mulss
2008 Apr 16
2
[LLVMdev] RFC: PowerPC tail call optimization patch
Hello Dale,
this is an updated version of the tail call optimization patch for
powerpc. could you have a look at it?
i added code to support ppc64 (untested, will try to get access to
ppc64 on a friend's machine).
incorporated evan's formatting suggestions. ;)
will run another round of testing (llvm-test) on my powerpc g4/800
when i get the okay to commit. testing on this machine takes
2006 Nov 15
0
[LLVMdev] LowerCALL (TargetLowering)
Hi Nickhil,
The Legalizer expects lower'd call is the node that produce the same
number of values as the non-lowered node. That's what the assertion
is checking.
Take a look at the LowerCall routine for any other targets. You will
see that in the non-void function case, it returns a MERGE_VALUES,
i.e. all the results merged along with the chain.
Cheers,
Evan
On Nov 15, 2006, at
2007 Sep 24
0
[LLVMdev] RFC: Tail call optimization X86
Hi Arnold,
This is a very good first step! Thanks! Comments below.
Evan
Index: test/CodeGen/X86/constant-pool-remat-0.ll
===================================================================
--- test/CodeGen/X86/constant-pool-remat-0.ll (revision 42247)
+++ test/CodeGen/X86/constant-pool-remat-0.ll (working copy)
@@ -1,8 +1,10 @@
; RUN: llvm-as < %s | llc -march=x86-64 | grep LCPI | count 3
;
2006 May 05
1
[LLVMdev] ExecutionEngine blew the stack ?
Hi Simon,
You're probably right. LLVM's instruction selector is recursive so it
can run out of stack space. Select_store used to have enormous stack
frame (thanks to some gcc issues), we had to do all kinds of tricks
to get it under control. I just took a look at it, it's around 0.7k.
It used to be around 20k on x86 Mac OS X.
It's also possible that it has gotten into a
2007 Sep 23
2
[LLVMdev] RFC: Tail call optimization X86
The patch is against revision 42247.
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2006 Dec 14
3
[LLVMdev] ThisCall / Compilation problems
Hi all,
A few things.
Firstly, I've got a working implementation of the X86ThisCall calling
convention, but I'm unsure how to go about submitting it.
(I'm not really sure how to go about creating patch files etc, but would
like to contribute to the project).
Also, I'm using MS Visual C++ Express, and there are a few things that stop
llvm1.9 (and the current CVS release) from
2008 Sep 08
0
[LLVMdev] adde/addc
Richard Pennington wrote:
> My target doesn't support 64 bit arithmetic, so I'd like to supply
> definitions for adde/addc. The problem is I can't seem to figure out the
> magic. Here's an example of what I need to generate:
>
> # two i64s in r5/r6 and r7/r8
> # result in r1/r2, carry in r3
>
> # adde
> add r2, r6, r8
> cmpltu r3, r2, r6 #
2008 Jul 10
2
[LLVMdev] Implementing llvm.atomic.cmp.swap.i32 on PowerPC
Cool, that worked. New patch attached...
Cheers,
Gary
Evan Cheng wrote:
> Just cast both values to const TargetRegisterClass*.
>
> Evan
>
> On Jul 10, 2008, at 7:36 AM, Gary Benson wrote:
> > Evan Cheng wrote:
> > > How about?
> > >
> > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass :
> > > &PPC:G8RCRegClass;
>
2008 Apr 22
0
[LLVMdev] RFC: PowerPC tail call optimization patch
On Apr 22, 2008, at 4:58 AM, Arnold Schwaighofer wrote:
> On Tue, Apr 22, 2008 at 12:30 AM, Evan Cheng <evan.cheng at apple.com>
> wrote:
>> More nitpicks:
>> ...
>> No need for else here. :-)
> Done
>> SPDiff = (int)CallerMinReservedArea - (int)ParamSize;
>>
>> Just change last statement to
>> int SPDiff = (int)...
> Done
>>
2007 Sep 11
0
[LLVMdev] RFC: Tail call optimization X86
Hi Arnold,
Thanks for the patch. Some questions and commons:
1. Have you test it against the llvm test suite? Does it work if fp
elimination optimization is turned off?
2. Please follow llvm coding convention and make sure every line fits
in 80 columns.
3.
enum NameDecorationStyle {
None,
StdCall,
- FastCall
+ FastCall,
+ FastCC // the normal fastcc calling convention
};
Why is