search for: sdnphaschain

...rt : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; def SDT_MYCallSeqEnd : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; def MYCallseqStart : SDNode<"ISD::CALLSEQ_START", SDT_MYCallSeqStart, [SDNPHasChain, SDNPOutGlue]>; def MYCallseqEnd : SDNode<"ISD::CALLSEQ_END", SDT_MYCallSeqEnd, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; def SDT_MYCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; def SDT_MYRet : SDT...

Hi, What does it mean if a custom Node in the instructions description file is declared to have a Chain? Looking at different backends, I have the impression that it describes some sort of side effect and usually used for nodes affecting the control flow. But I'm not quite sure. Can someone describe the semantics of this property and also what is a typical usage of it? In particular, I have

...DTCisVT<0, i32>, SDTCisVT<1, > i32>]>; > def SDT_MYCallSeqEnd : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, > i32>]>; > def MYCallseqStart : SDNode<"ISD::CALLSEQ_START", SDT_MYCallSeqStart, > [SDNPHasChain, SDNPOutGlue]>; > def MYCallseqEnd : SDNode<"ISD::CALLSEQ_END", SDT_MYCallSeqEnd, > [SDNPHasChain, SDNPOptInGlue, > SDNPOutGlue]>; > > def SDT_MYCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>; >...

...targets, but I’m missing something and can’t see what it is. I have simplified my TD description to just: def MyCallseqStart : SDNode<"ISD::CALLSEQ_START", SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>, [SDNPHasChain, SDNPOutGlue]>; def MyCallseqEnd : SDNode<"ISD::CALLSEQ_END", SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>, [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>; def my_call : SDNode<"MyISD::CALL",...

...g on an intrinsic function, which will write to a pointer argument. So I am lowering it and think I need to catch it in lowerINTRINSIC_W_CHAIN, but somehow it always fall into INTRINSIC_WO_CHAIN category. I put [IntrReadwriteArgMem] into my Intrinsic class definition, it did not help. tried put [SDNPHasChain] into intrinsic class definition, cause errors” Element type mismatch for list”. wondering how to flag it to INTRINSIC_W_CHAIN? best Kevin

Tks Tom, That is my confusing part. How can I make it to "access memory” so it will HasChain? Is there any flag set like in typeProfile, Node, instructions? myLoad, mayStore, SDNPHasChain? -kevin On Jul 18, 2014, at 4:26 PM, Tom Stellard <tom at stellard.net> wrote: > On Fri, Jul 18, 2014 at 04:15:45PM -0400, kewuzhang wrote: >> sure! >> >> class TEST_INTINSIC_FM< string asmstr> : Intrinsic >> <llvm_i32_ty], [llvm_i32_ty, llvm_ptr_ty],...

...>>>> So I am lowering it and think I need to catch it in lowerINTRINSIC_W_CHAIN, but somehow it always fall into INTRINSIC_WO_CHAIN category. >>>> >>>> I put [IntrReadwriteArgMem] into my Intrinsic class definition, it did not help. >>>> tried put [SDNPHasChain] into intrinsic class definition, cause errors” Element type mismatch for list”. >>>> >>>> wondering how to flag it to INTRINSIC_W_CHAIN? >>> >>> >>> Does it have chain in the initial DAG? >>> >>> -Krzysztof >>> &g...

...ll write to a pointer argument. >> So I am lowering it and think I need to catch it in lowerINTRINSIC_W_CHAIN, but somehow it always fall into INTRINSIC_WO_CHAIN category. >> >> I put [IntrReadwriteArgMem] into my Intrinsic class definition, it did not help. >> tried put [SDNPHasChain] into intrinsic class definition, cause errors” Element type mismatch for list”. >> >> wondering how to flag it to INTRINSIC_W_CHAIN? > > > Does it have chain in the initial DAG? > > -Krzysztof > > > -- > Qualcomm Innovation Center, Inc. is a member...

...peProfile<0, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1> +]>; + def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ SDTCisPtrTy<0>, SDTCisVT<1, i32> ]>; @@ -143,12 +149,22 @@ def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain, SDNPMayStore]>; +// Atomic operations +def PPCatomic_load_add : SDNode<"PPCISD::ATOMIC_LOAD_ADD", + SDT_PPCatomic_load_add, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; +def PPCatomic_cmp_swap : SDNode<"PPC...

PPCTargetLowering::EmitInstrWithCustomInserter has a reference to the current MachineFunction for other purposes. Can you use MachineFunction::getRegInfo instead? Dan On Jul 8, 2008, at 1:56 PM, Gary Benson wrote: > Would it be acceptable to change MachineInstr::getRegInfo from private > to public so I can use it from > PPCTargetLowering::EmitInstrWithCustomInserter? > >

...peProfile<0, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1> +]>; + def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ SDTCisPtrTy<0>, SDTCisVT<1, i32> ]>; @@ -143,12 +149,22 @@ def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain, SDNPMayStore]>; +// Atomic operations +def PPCatomic_load_add : SDNode<"PPCISD::ATOMIC_LOAD_ADD", + SDT_PPCatomic_load_add, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; +def PPCatomic_cmp_swap : SDNode<"PPC...

Hi Gary, This does not patch cleanly for me (PPCISelLowering.cpp). Can you prepare a updated patch? Thanks, Evan On Jul 10, 2008, at 11:45 AM, Gary Benson wrote: > Cool, that worked. New patch attached... > > Cheers, > Gary > > Evan Cheng wrote: >> Just cast both values to const TargetRegisterClass*. >> >> Evan >> >> On Jul 10, 2008, at 7:36

Just cast both values to const TargetRegisterClass*. Evan On Jul 10, 2008, at 7:36 AM, Gary Benson wrote: > Evan Cheng wrote: >> How about? >> >> const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : >> &PPC:G8RCRegClass; >> unsigned TmpReg = RegInfo.createVirtualRegister(RC); > > I tried something like that yesterday: > > const

Evan Cheng wrote: > How about? > > const TargetRegisterClass *RC = is64Bit ? &PPC:GPRCRegClass : > &PPC:G8RCRegClass; > unsigned TmpReg = RegInfo.createVirtualRegister(RC); I tried something like that yesterday: const TargetRegisterClass *RC = is64bit ? &PPC::GPRCRegClass : &PPC::G8RCRegClass; but I kept getting this error no matter how I arranged it:

You need to insert new basic blocks and update CFG to accomplish this. There is a hackish way to do this right now. Add a pseudo instruction to represent this operation and mark it usesCustomDAGSchedInserter. This means the intrinsic is mapped to a single (pseudo) node. But it is then expanded into instructions that can span multiple basic blocks. See

...peProfile<0, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1> +]>; + def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ SDTCisPtrTy<0>, SDTCisVT<1, i32> ]>; @@ -143,12 +149,22 @@ def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain, SDNPMayStore]>; +// Atomic operations +def PPCatomic_load_add : SDNode<"PPCISD::ATOMIC_LOAD_ADD", + SDT_PPCatomic_load_add, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; +def PPCatomic_cmp_swap : SDNode<"PPC...

Would it be acceptable to change MachineInstr::getRegInfo from private to public so I can use it from PPCTargetLowering::EmitInstrWithCustomInserter? Cheers, Gary Evan Cheng wrote: > Look for createVirtualRegister. These are examples in > PPCISelLowering.cpp. > > Evan > On Jul 8, 2008, at 8:24 AM, Gary Benson wrote: > > > Hi Evan, > > > > Evan Cheng wrote:

Chris Lattner wrote: > On Jun 27, 2008, at 8:27 AM, Gary Benson wrote: > > def CMP_UNRESw : Pseudo<(outs), (ins GPRC:$rA, GPRC:$rB, i32imm: > > $label), > > "cmpw $rA, $rB\n\tbne- La${label}_exit", > > [(PPCcmp_unres GPRC:$rA, GPRC:$rB, imm: > > $label)]>; > > } > > > > ...and

...for i32 only. def ADDR : ComplexPattern<i32, 2, "SelectADDR", [], []>; def MEM : Operand<i32> { let PrintMethod = "printMemOperand"; let MIOperandInfo = (ops GPR, GPR); } def global_st : SDNode<"AMDILISD::GLOBAL_STORE", SDTStore, [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>; def global_store : PatFrag<(ops node:$val, node:$ptr), (st node:$val, node:$ptr), [{ return isGlobalStore(dyn_cast<StoreSDNode>(N)); }]>; def GLOBALSTORE : OneInOneOut<IL_OP_MOV, (outs), (ins GPR:$val, MEM:$ptr),...

...peProfile<0, 2, [ + SDTCisInt<0>, SDTCisPtrTy<1> +]>; + def SDT_PPCTC_ret : SDTypeProfile<0, 2, [ SDTCisPtrTy<0>, SDTCisVT<1, i32> ]>; @@ -143,12 +149,22 @@ def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain, SDNPMayStore]>; +// Atomic operations +def PPCatomic_load_add : SDNode<"PPCISD::ATOMIC_LOAD_ADD", + SDT_PPCatomic_load_add, + [SDNPHasChain, SDNPMayLoad, SDNPMayStore]>; +def PPCatomic_cmp_swap : SDNode<"PPC...