search for: sdnodexforms

Hi Kevin, To get some portion of a constant immediate you can use SDNodeXForms to transform constant SDNodes into other values. For a worked example, in the MIPS backend we use this for constant synthesis by materializing the value into a register: (From lib/Target/MipsInstrInfo.td): // Transformation Function - get the lower 16 bits. def LO16 : SDNodeXForm<imm, [{ re...

Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the 'EXTRACT_SUBREG' but that seems to error at the end of scheduling. Looking at Target.td, I'm not sure which opcode is meant

Hello, Edd > > llvm[3]: Building ARM.td instruction selector implementation with tblgen > > assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node > > type!"" failed: file "CodeGenDAGPatterns.cpp", line 949, function > > "ApplyTypeConstraints" Could you please try with gcc 4.x and check, whether

Hello Tom, > I took a look at lib/CodeGen/SelectionDAG/LegalizeDAG.cpp and it > doesn't look like there is an Expand operation implemented for > ISD::Constant. I think you'll either need implement Expand for > ISD::Constant or Custom lower it in your backend. thank you for that information. This exactly is what I feared. Well I did some more mostly unguided hacking and these

Hi there, I am a student considering a compiler design based dissertation with llvm. I am having problems building llvm on OpenBSD-current. I hope to make a port of llvm for OpenBSD once I have figured out how to build it. Observe: llvm[3]: Compiling Deserialize.cpp for Release build In file included from /home/edd/llvm/llvm-2.3/include/llvm/Bitcode/BitstreamRead er.h:18, from

On Thu, Jun 12, 2008 at 7:02 PM, Edd Barrett <vext01 at gmail.com> wrote: > gcc4.2 works fine. But it only works fine for svn snapshots. Your most recent release does not build on OpenBSD with gcc-4.2. llvm[3]: Building ARM.td instruction selector implementation with tblgen assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5

On Thu, Jun 12, 2008 at 11:41 AM, Anton Korobeynikov <asl at math.spbu.ru> wrote: > Hello, Edd > >> > llvm[3]: Building ARM.td instruction selector implementation with tblgen >> > assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node >> > type!"" failed: file "CodeGenDAGPatterns.cpp", line

On Wed, Jun 11, 2008 at 11:49 AM, Gordon Henriksen <gordonhenriksen at mac.com> wrote: > Could you please update to r52213 or later in svn and check whether > this error is resolved with your gcc? Latest trunk fixes that error. Next problem :) llvm[3]: Building ARM.td register information header with tblgen llvm[3]: Building ARM.td register names with tblgen llvm[3]: Building ARM.td

On Mon, Jun 16, 2008 at 05:00:24PM +0100, Edd Barrett wrote: > On Thu, Jun 12, 2008 at 7:02 PM, Edd Barrett <vext01 at gmail.com> wrote: > > gcc4.2 works fine. > > But it only works fine for svn snapshots. Your most recent release > does not build on OpenBSD with gcc-4.2. > > llvm[3]: Building ARM.td instruction selector implementation with tblgen > assertion

Hi guys, Edd Barrett wrote: > Hi there, > > I am a student considering a compiler design based dissertation with > llvm. I am having problems building llvm on OpenBSD-current. I hope to > make a port of llvm for OpenBSD once I have figured out how to build > it. We still have not had any luck building llvm. Since last time, we have rebuilt gcc with -O0 incase of gcc

Hello, I am working on a AVR backend and have a version up and running that will convert LLVM IR code to assembly code for my target. I have written a bunch of instructions from the AVR Instruction Set in AVRInstrInfo.td and not much else. In a simple test case I am attempting to compile (if that is the word you are supposed to use for this operation) test.ll: define i8 @foo(i8 %a, i8 %b) {

Chris Lattner wrote: >>It is possible to write multi-instruction pattern, e.g. >>X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>Sounds like you want to define them as SDNodeXform that returns upper >>and lower 16 bits respectively. Take a look at PSxLDQ_imm in >>X86InstrSSE.td as an example. > > > Another good example is the PPC

On Jan 9, 2007, at 10:01 AM, Scott Michel wrote: > I was able to resolve my previous question about dealing with custom > loads/stores, and following Chris' suggestion, the IBM Cell SPU > backend > can generate code for "int main(void) { return 0; }" without crashing > llc. There's a lot of work still to be done... like getting frame > offsets correctly

On Apr 26, 2011, at 1:27 PM, Borja Ferrer wrote: > Hello Jim thanks for the reply, > > For normal additions with immediates I've done the same as ARM does, basically transforming add(x, imm) nodes to sub(x, -imm) with a pattern in the .td file like this: > def : Pat<(add DLDREGS:$src1, imm:$src2), > (SUBIWRdK DLDREGS:$src1, (imm16_neg_XFORM imm:$src2))>;

Thanks Jim, I've implemented the negation part successfully :) maybe the second part could be a possible feature request so others could use it aswell? 2011/4/27 Jim Grosbach <grosbach at apple.com> > > On Apr 26, 2011, at 1:27 PM, Borja Ferrer wrote: > > > Hello Jim thanks for the reply, > > > > For normal additions with immediates I've done the same as

...gt;, and using the same InstructionSelector we already have to reselect. To my surprise... not many changes are required to seemingly make this work: // fold loads in to compare instructions def : Pat<(CPw_sr i32:$k, (MOVw_wf iPTR:$s)), (CPw_sf i32:$k, iPTR:$s)>; And it looks like SDNodeXForms will work off the bat, along with complex renderers. The main catches being with constants that require checking (due G_CONSTANT being handled differently to immediates), along with needing to add checks that the instruction has the same implicits, and that they're dead where appropriate. But i...

I was able to resolve my previous question about dealing with custom loads/stores, and following Chris' suggestion, the IBM Cell SPU backend can generate code for "int main(void) { return 0; }" without crashing llc. There's a lot of work still to be done... like getting frame offsets correctly computed and hauling in the raft of intrinsics that the Cell SDK defines. Three quick

Chris Lattner wrote: > On Sep 23, 2008, at 11:26 AM, David Greene wrote: > >> Are there any examples of using tablegen to generate multiple machine >> instructions from a single pattern? Or do these cases always have >> to be >> manually expanded? > > PPC has a bunch of examples, for example: > > // Arbitrary immediate support. Implement in terms of

Hello Jim thanks for the reply, For normal additions with immediates I've done the same as ARM does, basically transforming add(x, imm) nodes to sub(x, -imm) with a pattern in the .td file like this: def : Pat<(add DLDREGS:$src1, imm:$src2), (SUBIWRdK DLDREGS:$src1, (imm16_neg_XFORM imm:$src2))>; Now, the typical pattern concerning additions with global addresses looks