search for: sdnodexform

Hi Kevin, To get some portion of a constant immediate you can use SDNodeXForms to transform constant SDNodes into other values. For a worked example, in the MIPS backend we use this for constant synthesis by materializing the value into a register: (From lib/Target/MipsInstrInfo.td): // Transformation Function - get the lower 16 bits. def LO16 : SDNodeXForm<imm, [{ r...

Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the 'EXTRACT_SUBREG' but that seems to error at the end of scheduling. Looking at Target.td, I'm not sure which opcode is meant

Hello, Edd > > llvm[3]: Building ARM.td instruction selector implementation with tblgen > > assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node > > type!"" failed: file "CodeGenDAGPatterns.cpp", line 949, function > > "ApplyTypeConstraints" Could you please try with gcc 4.x and check, whether this problem exists for you or not. -- With best regards, Anton Koro...

Hello Tom, > I took a look at lib/CodeGen/SelectionDAG/LegalizeDAG.cpp and it > doesn't look like there is an Expand operation implemented for > ISD::Constant. I think you'll either need implement Expand for > ISD::Constant or Custom lower it in your backend. thank you for that information. This exactly is what I feared. Well I did some more mostly unguided hacking and these

Hi there, I am a student considering a compiler design based dissertation with llvm. I am having problems building llvm on OpenBSD-current. I hope to make a port of llvm for OpenBSD once I have figured out how to build it. Observe: llvm[3]: Compiling Deserialize.cpp for Release build In file included from /home/edd/llvm/llvm-2.3/include/llvm/Bitcode/BitstreamRead er.h:18, from

...rrett <vext01 at gmail.com> wrote: > gcc4.2 works fine. But it only works fine for svn snapshots. Your most recent release does not build on OpenBSD with gcc-4.2. llvm[3]: Building ARM.td instruction selector implementation with tblgen assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node type!"" failed: file "CodeGenDAGPatterns.cpp", line 932, function "ApplyTypeConstraints" gmake[3]: *** [/usr/ports/devel/llvm/w-llvm-2.3/llvm-2.3/lib/Target/ARM/Release/ARMGenDAGISel.inc.tmp] Abort trap (core dumped) gmake[3]: Leavi...

...;> >> def : Pat<(i32 imm:$imm), >> (IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>; > > It is possible to write multi-instruction pattern, e.g. > X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? > Sounds like you want to define them as SDNodeXform that returns upper > and lower 16 bits respectively. Take a look at PSxLDQ_imm in > X86InstrSSE.td as an example. Another good example is the PPC backend, which has the exact same issue for integer constants. >> - The return instruction for Cell SPU is "bi $lr". How do I ja...

On Thu, Jun 12, 2008 at 11:41 AM, Anton Korobeynikov <asl at math.spbu.ru> wrote: > Hello, Edd > >> > llvm[3]: Building ARM.td instruction selector implementation with tblgen >> > assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node >> > type!"" failed: file "CodeGenDAGPatterns.cpp", line 949, function >> > "ApplyTypeConstraints" > Could you please try with gcc 4.x and check, whether this problem exists > for you or not. gcc4.2 works fi...

...lgen llvm[3]: Building ARM.td instruction names with tblgen llvm[3]: Building ARM.td instruction information with tblgen llvm[3]: Building ARM.td assembly writer with tblgen llvm[3]: Building ARM.td instruction selector implementation with tblgen assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node type!"" failed: file "CodeGenDAGPatterns.cpp", line 949, function "ApplyTypeConstraints" gmake[3]: *** [/tmp/llvm/lib/Target/ARM/Debug/ARMGenDAGISel.inc.tmp] Abort trap (core dumped) gmake[3]: Leaving directory `/tmp/llvm/lib/Target...

...rote: > > gcc4.2 works fine. > > But it only works fine for svn snapshots. Your most recent release > does not build on OpenBSD with gcc-4.2. > > llvm[3]: Building ARM.td instruction selector implementation with tblgen > assertion "getOperator()->isSubClassOf("SDNodeXForm") && "Unknown node > type!"" failed: file "CodeGenDAGPatterns.cpp", line 932, function > "ApplyTypeConstraints" > gmake[3]: *** [/usr/ports/devel/llvm/w-llvm-2.3/llvm-2.3/lib/Target/ARM/Release/ARMGenDAGISel.inc.tmp] > Abort trap (core dum...

...en it feels like it: #1 0x04e521a3 in abort () at /usr/src/lib/libc/stdlib/abort.c:68 #2 0x04df29d7 in __assert2 (file=0x3c0018e1 "CodeGenDAGPatterns.cpp", line=934, func=0x3c0020a6 "ApplyTypeConstraints", failedexpr=0x3c002400 "getOperator()->isSubClassOf(\"SDNodeXForm\") && \"Unknown node type!\"") at /usr/src/lib/libc/gen/assert.c:52 #3 0x1c0d0bcd in llvm::TreePatternNode::ApplyTypeConstraints (this=0x7dfc0700, TP=@0x7c0fb6c0, NotRegisters=false) at CodeGenDAGPatterns.cpp:934 #4 0x1c0cfb6b in llvm::TreePatternNode::ApplyTypeConstra...

Hello, I am working on a AVR backend and have a version up and running that will convert LLVM IR code to assembly code for my target. I have written a bunch of instructions from the AVR Instruction Set in AVRInstrInfo.td and not much else. In a simple test case I am attempting to compile (if that is the word you are supposed to use for this operation) test.ll: define i8 @foo(i8 %a, i8 %b) {

Chris Lattner wrote: >>It is possible to write multi-instruction pattern, e.g. >>X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? >>Sounds like you want to define them as SDNodeXform that returns upper >>and lower 16 bits respectively. Take a look at PSxLDQ_imm in >>X86InstrSSE.td as an example. > > > Another good example is the PPC backend, which has the exact same issue > for integer constants. Actually, for SPU, not quite the same: def ILHU : RI1...

...5 > > I tried: > > def : Pat<(i32 imm:$imm), > (IOHL (ILHU (HI16 imm:$imm)), (LO16 imm:$imm))>; It is possible to write multi-instruction pattern, e.g. X86InstrSSE.td line 1911. But how are you defining HI16 and LO16? Sounds like you want to define them as SDNodeXform that returns upper and lower 16 bits respectively. Take a look at PSxLDQ_imm in X86InstrSSE.td as an example. > > - The return instruction for Cell SPU is "bi $lr". How do I jam that > into the instruction info w/o tblgen bitching up a storm about the > "$"...

...ng patterns, if it's even possible. The obvious hack is adding a "-" char when lowering the symbol reference into text. > You can probably do some of this with a complex pattern that has a transform function. Something like (completely untested, etc): def neg_tglobaladdr_XFORM : SDNodeXForm<tglobaladdr, [{return makeNegatedGlobalAddr(CurDAG);}]>; def neg_tglobaladdr : PatLeaf<(tglobaladdr), [{ return <true if the curdag really is a tglobaladdr, false otherwise>; }], neg_tglobaladdr_XFORM>; def : Pat<(add DREGS:$src, (Wrapper tglobaladdr:$src2)),...

...ssible. The obvious hack is adding a "-" char when lowering the > symbol reference into text. > > > > You can probably do some of this with a complex pattern that has a > transform function. Something like (completely untested, etc): > > def neg_tglobaladdr_XFORM : SDNodeXForm<tglobaladdr, [{return > makeNegatedGlobalAddr(CurDAG);}]>; > def neg_tglobaladdr : PatLeaf<(tglobaladdr), [{ > return <true if the curdag really is a tglobaladdr, false otherwise>; > }], neg_tglobaladdr_XFORM>; > > def : Pat<(add DREGS:$src, (Wrapper tglo...

...gt;, and using the same InstructionSelector we already have to reselect. To my surprise... not many changes are required to seemingly make this work: // fold loads in to compare instructions def : Pat<(CPw_sr i32:$k, (MOVw_wf iPTR:$s)), (CPw_sf i32:$k, iPTR:$s)>; And it looks like SDNodeXForms will work off the bat, along with complex renderers. The main catches being with constants that require checking (due G_CONSTANT being handled differently to immediates), along with needing to add checks that the instruction has the same implicits, and that they're dead where appropriate. But...

I was able to resolve my previous question about dealing with custom loads/stores, and following Chris' suggestion, the IBM Cell SPU backend can generate code for "int main(void) { return 0; }" without crashing llc. There's a lot of work still to be done... like getting frame offsets correctly computed and hauling in the raft of intrinsics that the Cell SDK defines. Three quick

...(f32 FR32:$src)>; (this is actually a very useful and important pattern, I wish it was available!) I had actually written my pattern in a similar style before I found this. When I tried to build, tblgen complained about the pattern being of an unknown type (didn't match Instruction or SDNodeXForm). I'm assuming there's some missing tblgen support here and that's why this pattern is commented out. Is that right? Are there plans to add tblgen support for these kinds of patterns? -Dave

Hello Jim thanks for the reply, For normal additions with immediates I've done the same as ARM does, basically transforming add(x, imm) nodes to sub(x, -imm) with a pattern in the .td file like this: def : Pat<(add DLDREGS:$src1, imm:$src2), (SUBIWRdK DLDREGS:$src1, (imm16_neg_XFORM imm:$src2))>; Now, the typical pattern concerning additions with global addresses looks