Displaying 20 results from an estimated 42 matches for "sdlocs".
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2017 Jul 29
2
ISelDAGToDAG breaks node ordering
Hi,
During instruction selection, I have the following code for certain LOAD
instructions:
const LoadSDNode *LD = cast<LoadSDNode>(N);
SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT,
PtrVT, MVT::Other,
LD->getBasePtr(), LD->getChain());
// Honestly, I have no idea what this does, but other memory
// accessing instructions
2018 Apr 10
1
64 bit mask in x86vshuffle instruction
Please tell me whether the following implementation is correct.....
My target supports 64 bit mask means immediate(0-2^63)
I have implemented it but i dont know whether its correct or not. Please
see the changes below that i have made in x86isellowering.cpp
static SDValue lower2048BitVectorShuffle(const SDLoc &DL, ArrayRef<int>
Mask,
MVT VT,
2015 Mar 09
2
[LLVMdev] LLVM Backend DAGToDAGISel INTRINSIC
I am currently working on DAGToDAGISel class for MIPS and am trying to
figure out a way to use INTRINSIC_W_CHAIN for an intrinsic which can return
a value.
My intrinsic is defined as:
Intrinsic<[llvm_i32_ty],[llvm_i32_ty,llvm_i32_ty,llvm_i32_ty,llvm_i32_ty],[IntrReadWriteArgMem]>;
i.e. it has four arguments and one return value
In DAGToDAGISel when I try to pass it with four arguments and
2017 Jul 31
0
ISelDAGToDAG breaks node ordering
On 7/29/2017 1:28 AM, Dr. ERDI Gergo via llvm-dev wrote:
> Hi,
>
> During instruction selection, I have the following code for certain
> LOAD instructions:
>
> const LoadSDNode *LD = cast<LoadSDNode>(N);
> SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N),
> VT, PtrVT, MVT::Other,
> LD->getBasePtr(), LD->getChain());
>
2013 May 26
0
[LLVMdev] SelectionDAG Preserves IR Order
I want to make folks aware of Xiaoyi's fixes to SelectionDAG. They ensure that all SelectionDAG nodes, except for constants and such, are assigned an order which is propagated through the SD passes. This fixes the problem of debug information being dropped by SelectionDAG. I'm particularly happy because it means that -pre-RA-sched=source now works the way it was meant to. This means I can
2017 Dec 24
4
Canonical way to handle zero registers?
Thanks, that sounds like it would work. Was this based on what any other
target did? Or do any other targets take this approach?
I just want to make sure that we don't already have a hook suitable for
this. Overriding runOnFunction to run what could be described as just a
"late SelectionDAG pass" sounds pretty intrusive. Do you remember other
approaches that didn't work?
--
2016 Jun 24
2
creating Intrinsic DAG Node
The intrinsic ID is an int, not a float.
—escha
> On Jun 24, 2016, at 7:49 AM, Ryan Taylor via llvm-dev <llvm-dev at lists.llvm.org> wrote:
>
> given the following C code:
>
> float b=16, a=0;
> int main() {
> float a = sqrt(b);
> return0;
> }
>
> I'm trying to lower FSQRT down, but getting a casting issue, my code is:
>
> SDValue
2016 Jun 24
3
creating Intrinsic DAG Node
I've tried all the types (both for result and Intrinsic ID), can't seem to
find what cast is causing the issue here.
On Fri, Jun 24, 2016 at 11:47 AM, Ryan Taylor <ryta1203 at gmail.com> wrote:
> That's what I thought but I got the same error with:
>
> DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
> DAG.getTargetConstant(Intrinsic::my_intrinsic, DL, MVT::i16), LHS);
2015 Jan 19
6
[LLVMdev] X86TargetLowering::LowerToBT
I'm tracking down an X86 code generation malfeasance regarding BT (bit
test) and I have some questions.
This IR *matches* and then *X86TargetLowering::LowerToBT **is called:*
%and = and i64 %shl, %val * ; (val & (1 << index)) != 0 ; *bit test
with a *register* index
This IR *does not match* and so *X86TargetLowering::LowerToBT **is not
called:*
%and = lshr i64 %val, 25
2019 Apr 03
2
Inline ASM Question
The code below is triggering some weird behavior that's different from how
gcc treats this inline asm. Clang keeps the original type of "loc" as
"bool", which generates an "i1 true" after inlining. So far so good.
However, during ISEL, the "true" is converted to a signed integer. So when
it's evaluated, the result is this:
.quad
2016 Feb 02
3
creating Intrinsic DAG Node
Matt,
This seems to generate llvm.my_intrinsic just fine in the DAG, so no DAG
errors; however, it won't match. For example, if I call the intrinsic from
C, the DAG node looks to be named the same in dotty file but it won't
match... am I missing something?
I've done it exactly the way it was done above. The DAG looks great but
it won't match. Did I miss something?
Thanks.
2017 Dec 26
2
Canonical way to handle zero registers?
Thanks! That looks like a winning approach.
I swear I grepped around for ISD::Constant but for some reason never found
this code. I think maybe I was searching for ISD::Constant with
setOperationAction, which in hindsight was narrowing down my search to just
lowering, which is exactly what I didn't want! (I was looking for other
approaches). I also tried looking in depth at PowerPC but it
2016 Feb 02
2
creating Intrinsic DAG Node
Matt,
The added intrinsic in DAG looks like:
0xbedb698: i32 = llvm.MyIntrinsic 0xbedb200, 0xbedac18 [ORD=4]
The builtin in DAG looks like:
0xbedb2a8: i32,ch = llvm 0xbedb158:1, 0xbedb200, 0xbedb158 [ORD=7] [ID=16]
The only difference I'm seeing is the extra operand, which is a 'ch'
from a load.
On Tue, Feb 2, 2016 at 3:55 PM, Matt Arsenault <arsenm2 at gmail.com>
2017 May 30
1
Pseudo-instruction that overwrites its input register
The reason the ones in PPCInstrInfo.td don't have the patterns to match is
the reason they are more analogous to your problem. Namely, tblgen does not
have a way to produce nodes with more than one result. The load-with-update
instructions do exactly that - one of the inputs is also an output, but the
other output is independent (and necessarily a separate register). The FMA
variants have
2014 Feb 08
2
[LLVMdev] selecting ISD node - help
Hey, I wanted to add an intrinsics to read MSRs.
So I added the intrinsics and lowered it to a new ISD node I created
ISD::RDMSR, its first operand is the MSR id.
I added a case in X86DAGToDAGISel::Select for ISD::RDMSR.
Now I know rdmsr works like so:
mov r/ecx, <id>
rdmsr
r/eax holds the lower 32/64 bit
>From what I understood this needs a Token Factor node, nodes which are
2014 Mar 07
3
[LLVMdev] [RFC] Add second "failure" AtomicOrdering to cmpxchg instruction
Hi all,
The C++11 (& C11) compare_exchange functions with explicit memory
order allow you to specify two sets of semantics, one for when the
exchange actually happens and one for when it fails. Unfortunately, at
the moment the LLVM IR "cmpxchg" instruction only has one ordering,
which means we get sub-optimal codegen.
This probably affects all architectures which use
2016 Jun 04
4
Gluing arbitrary nodes together
Hello all,
I am working on adding atomics support to the AVR backend.
Because the target can only have one core, it is sufficient to:
- Save the status register
- Disable interrupts
- Do the nonatomic LOAD/STORE/SWAP/ADD
- Restore the status register
I’d really like to be able to do this at the IR level. What I want to do is
write a custom lowering hook to convert ISD::ATOMIC_LOAD
2016 Mar 28
0
RFC: atomic operations on SI+
On Fri, Mar 25, 2016 at 02:22:11PM -0400, Jan Vesely wrote:
> Hi Tom, Matt,
>
> I'm working on a project that needs few coherent atomic operations (HSA
> mode: load, store, compare-and-swap) for std::atomic_uint in HCC.
>
> the attached patch implements atomic compare and swap for SI+
> (untested). I tried to stay within what was available, but there are
> few issues
2015 Jan 19
2
[LLVMdev] X86TargetLowering::LowerToBT
Sure. Attached is the file but here are the functions. The first uses a
fixed bit offset. The second has a indexed bit offset. Compiling with llc
-O3, LLVM version 3.7.0svn, it compiles the IR from IsBitSetB() using btq %rsi,
%rdi. Good. But then it compiles IsBitSetA() with shrq/andq, which is is
pretty much what Clang had generated as IR.
shrq $25, %rdi
andq $1, %rdi
LLVM should be able to
2014 Oct 29
2
[LLVMdev] Virtual register def doesn't dominate all uses
Hi Quentin,
yes, this happens quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer".
I do have a very simple DAGToDAGISel::Select() method:
SDNode *MyTargetDAGToDAGISel::Select(SDNode *N)
{
SDLoc dl(N);
// default implementation
if (N -> isMachineOpcode()) {
N -> setNodeId(-1);
return NULL; // Already selected.
}
SDNode