search for: sdloc

Hi, During instruction selection, I have the following code for certain LOAD instructions: const LoadSDNode *LD = cast<LoadSDNode>(N); SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), VT, PtrVT, MVT::Other, LD->getBasePtr(), LD->getChain()); // Honestly, I have no idea what this does, but other memory // accessing instructions have something similar... MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsArray(1); MemOp[0]...

...tell me whether the following implementation is correct..... My target supports 64 bit mask means immediate(0-2^63) I have implemented it but i dont know whether its correct or not. Please see the changes below that i have made in x86isellowering.cpp static SDValue lower2048BitVectorShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT, SDValue V1, SDValue V2, const SmallBitVector &Zeroable, const X86Subtarget &Subtarget, S...

...SDValue op1 = Node->getOperand(3); SDValue op2= Node->getOperand(4); SDValue op3 = Node->getOperand(5); SDValue Ops[]= { op0, op1, op2, op3, Zero, ChainIn }; SDNode *Result = CurDAG->getMachineNode(Mips::BWT_DROP_RESULT, SDLoc(Node), ReturnValueVT, Ops); ReplaceUses(Node, Result); return std::make_pair(true, Result); Any clues on how INTRINSIC_W_CHAIN differs from INTRINSIC_VOID? Thanks, Ambuj Agrawal -------------- next part -------------- An HTML att...

...n 7/29/2017 1:28 AM, Dr. ERDI Gergo via llvm-dev wrote: > Hi, > > During instruction selection, I have the following code for certain > LOAD instructions: > > const LoadSDNode *LD = cast<LoadSDNode>(N); > SDNode* LDW = CurDAG->getMachineNode(AVR::LDWRdPtr, SDLoc(N), > VT, PtrVT, MVT::Other, > LD->getBasePtr(), LD->getChain()); > > // Honestly, I have no idea what this does, but other memory > // accessing instructions have something similar... > MachineSDNode::mmo_iterator MemOp = MF->allocateMemRefsA...

...s as: r182701,r182703,r182704,182706. Beware that out-of-tree targets will see merge conflicts in <Tgt>ISelDAGToDAG.cpp and <Tgt>ISelLowering.cpp. These should be trivial to resolve with a regex replace something like this: 's/DebugLoc dl = ([^.]+)\.getNode\(\)->getDebugLoc\(\)/SDLoc dl(\1)/g' then 's/([[:alnum:]]+)\.getDebugLoc\(\)/SDLoc(\1)/g' -Andy

Thanks, that sounds like it would work. Was this based on what any other target did? Or do any other targets take this approach? I just want to make sure that we don't already have a hook suitable for this. Overriding runOnFunction to run what could be described as just a "late SelectionDAG pass" sounds pretty intrusive. Do you remember other approaches that didn't work? --

...he following C code: > > float b=16, a=0; > int main() { > float a = sqrt(b); > return0; > } > > I'm trying to lower FSQRT down, but getting a casting issue, my code is: > > SDValue XXXLowering::LowerFSQRT(SDValue Op, SelectionDAG &DAG) const { > SDLoc DL(Op); > EVT VT = Op.getValueType(); > SDValue LHS = Op.getOperand(0); > > SDValue newNode = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, DAG.getTargetConstantFP(Intrinsic::my_intrinsic, DL, VT), LHS); > return newNode; > } > > The error I'm getting is: As...

...oat b=16, a=0; >> int main() { >> float a = sqrt(b); >> return0; >> } >> >> I'm trying to lower FSQRT down, but getting a casting issue, my code is: >> >> SDValue XXXLowering::LowerFSQRT(SDValue Op, SelectionDAG &DAG) const { >> SDLoc DL(Op); >> EVT VT = Op.getValueType(); >> SDValue LHS = Op.getOperand(0); >> >> SDValue newNode = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, >> DAG.getTargetConstantFP(Intrinsic::my_intrinsic, DL, VT), LHS); >> return newNode; >> } >> &g...

...d be to match *lshr reg/imm* first and then if the *following* instruction was an *and reg,1 *replace both with a BT*. *It doesn't look like *LowerToBT* as is can do that right now since it is matching the *and* instruction. SDValue X86TargetLowering::LowerToBT(*SDValue And*, ISD::CondCode CC, SDLoc dl, SelectionDAG &DAG) const { ... } But I think this is better done in a subclass of *CodeGen/PeepholeOptimizer.cpp.* thanks. -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150118/f4aae20d/attachment...

The code below is triggering some weird behavior that's different from how gcc treats this inline asm. Clang keeps the original type of "loc" as "bool", which generates an "i1 true" after inlining. So far so good. However, during ISEL, the "true" is converted to a signed integer. So when it's evaluated, the result is this: .quad

Matt, This seems to generate llvm.my_intrinsic just fine in the DAG, so no DAG errors; however, it won't match. For example, if I call the intrinsic from C, the DAG node looks to be named the same in dotty file but it won't match... am I missing something? I've done it exactly the way it was done above. The DAG looks great but it won't match. Did I miss something? Thanks.

...de); // Materialize zero constants as copies from R0. This allows the coalescer // to propagate these into other instructions. if (ConstNode->isNullValue()) { SDValue New = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), SDLoc(Node), Lanai::R0, MVT::i32); return ReplaceNode(Node, New.getNode()); } // Materialize all ones constants as copies from R1. This allows the // coalescer to propagate these into other instructions. if (ConstNode->isAllOnesValue()) { SDValue New = CurDAG-&g...

Matt, The added intrinsic in DAG looks like: 0xbedb698: i32 = llvm.MyIntrinsic 0xbedb200, 0xbedac18 [ORD=4] The builtin in DAG looks like: 0xbedb2a8: i32,ch = llvm 0xbedb158:1, 0xbedb200, 0xbedb158 [ORD=7] [ID=16] The only difference I'm seeing is the extra operand, which is a 'ch' from a load. On Tue, Feb 2, 2016 at 3:55 PM, Matt Arsenault <arsenm2 at gmail.com>

The reason the ones in PPCInstrInfo.td don't have the patterns to match is the reason they are more analogous to your problem. Namely, tblgen does not have a way to produce nodes with more than one result. The load-with-update instructions do exactly that - one of the inputs is also an output, but the other output is independent (and necessarily a separate register). The FMA variants have

...SR. Now I know rdmsr works like so: mov r/ecx, <id> rdmsr r/eax holds the lower 32/64 bit >From what I understood this needs a Token Factor node, nodes which are dependent on each other? case X86ISD::RDMSR: { unsigned idReg; SDValue idRegValue; unsigned resultReg; SDLoc dl = SDLoc(Node); SDValue id = Node->getOperand(0); EVT resultType = Node->getValueType(0); if(Subtarget->is64Bit()) { idReg = X86::RCX; resultReg = X86::RAX; } else { idReg = X86::ECX; resultReg = X86::EAX; } idRegValue = CurDAG->getRegiste...

...""""" diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index adba296..a30656a 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -692,12 +692,14 @@ public: SDValue getAtomic(unsigned Opcode, SDLoc dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachinePointerInfo PtrInfo, unsigned Alignment, - AtomicOrdering Ordering, + AtomicOrdering SuccessOrdering, + AtomicOrdering Failu...

...// Disable interrupts (`clr` is equivalent to `bclr 7`). auto ClearInterrupts = DAG.getNode(AVRISD::BCLR, DL, MVT::Glue, DAG.getConstant(7, DL, MVT::i8)); // Perform the nonatomic load. auto *Node = cast<AtomicSDNode>(AtomicOp.getNode()); SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, SDLoc(AtomicOp), AtomicOp.getValueType(), Node->getChain(), Node->getBasePtr(), Node->getMemoryVT(), Node->getMemOperand()); auto Restore = DAG.getCopyToReg(DAG.getEntryNode(), DL, AVR::SREG, Save); return Load; I can’t...

...t; case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG); > } > @@ -1680,6 +1687,40 @@ SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op, > } > } > > +SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const > +{ > + SDLoc DL(Op); > + > + AtomicSDNode *Swap = cast<AtomicSDNode>(Op); > + assert(Swap && Swap->isCompareAndSwap()); > + > + EVT MemVT = Swap->getMemoryVT(); > + EVT ValVT = EVT::getVectorVT(*DAG.getContext(), MemVT, 2); > + SDValue Cmp = Op.getOperand(2); > +...

...first > and then if the *following* instruction was an *and reg,1 *replace both > with a BT*. *It doesn't look like *LowerToBT* as is can do that right now > since it is matching the *and* instruction. > > SDValue X86TargetLowering::LowerToBT(*SDValue And*, ISD::CondCode CC, > SDLoc dl, SelectionDAG &DAG) const { ... } > > > But I think this is better done in a subclass of > *CodeGen/PeepholeOptimizer.cpp.* > > thanks. > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llv...

Hi Quentin, yes, this happens quite late. With the Option --debug-pass=Structure it's in or after "Assembly Printer". I do have a very simple DAGToDAGISel::Select() method: SDNode *MyTargetDAGToDAGISel::Select(SDNode *N) { SDLoc dl(N); // default implementation if (N -> isMachineOpcode()) { N -> setNodeId(-1); return NULL; // Already selected. } SDNode *res = SelectCode(N); return res; } Is that too simple? There are no further passes that eliminate anything. Anyway, I have another test progra...