search for: scopes

libswfdec/swfdec_as_function.c | 9 test/trace/Makefile.am | 117 ++++++++++ test/trace/scope-chain-did-you-understand-5.swf |binary test/trace/scope-chain-did-you-understand-5.swf.trace | 1 test/trace/scope-chain-did-you-understand-6.swf |binary

Lables: Gateway = 209.5.171.65 Netmask = 255.255.255.192 Eth0 = net = 209.5.171.66 Eth1 = loc = 192.168.0.1 There is no NAT clients, in essence loc is dmz. I can rename loc to dmz if that helps. Proxy/ARP is used for IP addresses 209.5.171.67-126 Problem: Using the Shorewall Action AllowFTP does not result in desired behavior when connecting from Internet to machines behind firewall in DMZ. From

On Mon, Jun 19, 2017 at 12:06 PM, Mehdi AMINI <joker.eph at gmail.com> wrote: > Hi, > > 2017-06-19 8:45 GMT-07:00 Andrew Kelley via llvm-dev < > llvm-dev at lists.llvm.org>: > >> Greetings, >> >> I have a Zig implementation of ceil which is emitted into LLVM IR like >> this: >> >> ; Function Attrs: nobuiltin nounwind >> define

Hi, I'd like to understand the order in which patterns are searched during ISEL. In the example below, indices are searched in ascending order from 808 to 3305, then it goes back to 3259 and eventually it matches the wrong instruction. Why did go back from 3305 to 3259? In my XXXGenDAGISel.inc, I can see that the correct instruction is at index 3420 but it never got there. ISEL: Starting

Hi, I would like to return a combination of named scopes in a named scope : For example, I have a named scope filter and I want to add a named scope eval_filters like Product.eval_filters([''x'',''y'',''z'']) is equivalent to Product.filter(''x'').filter(''y'').filter('...

Hi, I get build errors when trying to build a fresh r139985. Anyone got a clue? carl at carl:~/Downloads/llvm3.0/llvm$ gcc --version gcc (Ubuntu/Linaro 4.5.2-8ubuntu4) 4.5.2 Copyright (C) 2010 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. carl at

libswfdec/swfdec_script.c | 15 ++++++++++--- test/image/Makefile.am | 6 ++++- test/image/bw.jpg |binary test/image/image.c | 1 test/image/negative-color-transform.c | 32 ++++++++++++++++++++++++++++ test/image/negative-color-transform.swf |binary

...: preserving the existing 'noalias' attributes on pointers after inlining. My original proposal was technically flawed, and based on the original feedback, and subsequent discussions with Arnold and Andy, a new scheme has emerged: First, we'll add some metadata to define a hierarchy of scopes. For preserving noalias during function inlining, the inliner will fabricate a unique scope node for the inlined function (and then tag all memory accesses in the function). For use in representing C99 restrict pointers, a scope may represent the entire function, or some other statement block withi...

-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello! I have a problem with a duplicate route entry, when using a pre-installed route and automatic take-over by the "heartbeat" daemon, which adds an address and the kernel adds an route automatically. Maybe anyone has an explanation... > ip addr 1: lo: <LOOPBACK,UP> mtu 16436 qdisc noqueue inet 127.0.0.1/8 scope host lo

I have a setup with two Internet providers. One circuit (net0 == eth1) is used primarily for employees and tunnels to other sites. The other (net1 == eth2) is for the production machines that customers access. Everythung works in teh sense that packets get to where they are sent (mostly) but I recently I had a sniffer on the system and noticed a problem I cannot solve. traffic coming in

...11/15/2014 12:08 AM, Tom Stellard wrote: > Can you send a plain-text version of this email. It's easier to read > and reply to. Sorry about that! Here's the plain text (I hope!): Hi all, OpenCL 2.0 introduced the notion of memory scope in atomic operations to global memory. These scopes are a hint to the underlying platform to optimize how synchronization is achieved. HSAIL also has a notion of memory scopes that is compatible with OpenCL 2.0. Currently, the LLVM IR uses a binary value (SingleThread/CrossThread) to represent synchronization scope on atomic instructions. This m...

using `opt --print-after-all -O3` I see that EarlyCSE is interpreting the call to `ceil` and constant fold: *** IR Dump After Early CSE *** ; Function Attrs: nobuiltin nounwind define i1 @do_test() #2 { Entry: %0 = call fastcc float @ceil(float 0.000000e+00) #6 %1 = call fastcc float @ceil32(float 0.000000e+00) #6 %2 = fcmp fast oeq float 0.000000e+00, %1 ret i1 %2 } So just running `opt

Thank you. i understood how avx512 vector instructions are written in x86instravx512. i need to define my vector instructions so i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))],

...'noalias' attributes on pointers after inlining. My > original proposal was technically flawed, and based on the original > feedback, and subsequent discussions with Arnold and Andy, a new > scheme has emerged: > > First, we'll add some metadata to define a hierarchy of scopes. For > preserving noalias during function inlining, the inliner will > fabricate a unique scope node for the inlined function (and then tag > all memory accesses in the function). For use in representing C99 > restrict pointers, a scope may represent the entire function, or > some ot...

Thank you; i have changed as follows.is it fine now? def VADD_256B : I<0xFE, MRMDestReg, (outs VR2048:$dst), (ins VR2048:$src1, VR2048:$src2), "VADD_256B\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (add VR2048:$src1, VR2048:$src2))]]>; Also here i have changed class RI to I. Does it make any difference? On Sat, Jul 8, 2017 at 9:38 AM, Craig Topper

Hi all, Currently, the LLVM IR uses a binary value (SingleThread/CrossThread) to represent synchronization scope on atomic instructions. We would like to enhance the representation of memory scopes in LLVM IR to allow more values than just the current two. The intention of this email is to invite comments on our proposal. There are some discussion before and it can be found here: https://groups.google.com/forum/#!searchin/llvm-dev/hsail/llvm-dev/46eEpS5h0E4/i3T9xw-DNVYJ Here is our new prop...

Hi Sameer, > On Jan 5, 2015, at 4:51 AM, Sahasrabuddhe, Sameer <Sameer.Sahasrabuddhe at amd.com> wrote: > > Right. The second version of my patches fixes the bitcode encoding. But now I see another potential problem with future bitcode if we require an ordering on the scopes. What happens when a backend later introduces a new scope that goes into the middle of the order? If they renumber the scopes to accomodate this, then existing bitcode for that backend will no longer work. The bitcode reader/writer cannot compensate for this since the values are backend-specific. I...

Hi All,   I have question regarding lexical scope information.   If I have .c source with scope as below. void func() {    //-- some code here..    { //parent scope       if() //high pass       {          int i;          for( i =0; i < FRAM_I; i++)          {          }       }       if() //low pass       {          int i;          for( i =0; i < FRAM_J; i++)          {          }       }

Greetings, I have a Zig implementation of ceil which is emitted into LLVM IR like this: ; Function Attrs: nobuiltin nounwind define internal fastcc float @ceil(float) unnamed_addr #3 !dbg !644 { Entry: %x = alloca float, align 4 store float %0, float* %x call void @llvm.dbg.declare(metadata float* %x, metadata !649, metadata !494), !dbg !651 %1 = load float, float* %x, !dbg !652 %2 =