search for: scope

libswfdec/swfdec_as_function.c | 9 test/trace/Makefile.am | 117 ++++++++++ test/trace/scope-chain-did-you-understand-5.swf |binary test/trace/scope-chain-did-you-understand-5.swf.trace | 1 test/trace/scope-chain-did-you-understand-6.swf |binary test/trace/scope-chain-did-you-understand-6.swf.trace | 1 test/tra...

...or pasv transfers fail. I had to manually open the ftp-data and the high ports to allow my clients to ftp in. Shorewall version 2.2.4 ip addr show 1: lo: <LOOPBACK,UP> mtu 16436 qdisc noqueue link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 inet 127.0.0.1/8 brd 127.255.255.255 scope host lo inet6 ::1/128 scope host valid_lft forever preferred_lft forever 2: eth0: <BROADCAST,MULTICAST,UP> mtu 1500 qdisc pfifo_fast qlen 1000 link/ether 00:a0:d2:1c:aa:13 brd ff:ff:ff:ff:ff:ff inet 209.5.171.66/26 brd 209.5.171.127 scope global eth0 inet6 fe80::2a0:d2f...

..._C99, file: !2, producer: "zig 0.0.0", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, enums: !3, globals: !12) !2 = !DIFile(filename: "test", directory: ".") !3 = !{!4} !4 = !DICompositeType(tag: DW_TAG_enumeration_type, name: "GlobalLinkage", scope: !5, file: !5, line: 126, baseType: !6, size: 8, align: 8, elements: !7) !5 = !DIFile(filename: "builtin.zig", directory: "/home/andy/dev/zig/build/zig-cache") !6 = !DIBasicType(name: "u8", size: 8, encoding: DW_ATE_unsigned_char) !7 = !{!8, !9, !10, !11} !8 = !DIEnume...

...earched in ascending order from 808 to 3305, then it goes back to 3259 and eventually it matches the wrong instruction. Why did go back from 3305 to 3259? In my XXXGenDAGISel.inc, I can see that the correct instruction is at index 3420 but it never got there. ISEL: Starting pattern match Skipped scope entry (due to false predicate) at index 3, continuing at 808 Skipped scope entry (due to false predicate) at index 809, continuing at 865 Skipped scope entry (due to false predicate) at index 867, continuing at 1091 Skipped scope entry (due to false predicate) at index 1093, continuing at 157...

Hi, I would like to return a combination of named scopes in a named scope : For example, I have a named scope filter and I want to add a named scope eval_filters like Product.eval_filters([''x'',''y'',''z'']) is equivalent to Product.filter(''x'').filter(''y'').filter('...

...Asserts build llvm[1]: Compiling DeltaAlgorithm.cpp for Debug+Asserts build llvm[1]: Compiling Disassembler.cpp for Debug+Asserts build In file included from CommandLine.cpp:25: /home/carl/Downloads/llvm3.0/llvm/include/llvm/Support/system_error.h:499: error: ‘EAFNOSUPPORT’ was not declared in this scope /home/carl/Downloads/llvm3.0/llvm/include/llvm/Support/system_error.h:500: error: ‘EADDRINUSE’ was not declared in this scope /home/carl/Downloads/llvm3.0/llvm/include/llvm/Support/system_error.h:501: error: ‘EADDRNOTAVAIL’ was not declared in this scope /home/carl/Downloads/llvm3.0/llvm/include/ll...

...| 1 test/image/negative-color-transform.c | 32 ++++++++++++++++++++++++++++ test/image/negative-color-transform.swf |binary test/image/negative-color-transform.swf.png |binary test/trace/Makefile.am | 7 ++++++ test/trace/function-scope-5.swf |binary test/trace/function-scope-5.swf.trace | 3 ++ test/trace/function-scope-6.swf |binary test/trace/function-scope-6.swf.trace | 3 ++ test/trace/function-scope-7.swf |binary test/trace/function-scope-7.swf.trace | 3 ++ t...

Hello everyone, In December, I had started a thread on scoped no-alias metadata in order to represent C99 'restrict' pointer information at the IR level: http://lists.cs.uiuc.edu/pipermail/llvmdev/2012-December/056586.html At this point, we also have another important use case: preserving the existing 'noalias' attributes on pointers after i...

...cate route entry, when using a pre-installed route and automatic take-over by the "heartbeat" daemon, which adds an address and the kernel adds an route automatically. Maybe anyone has an explanation... > ip addr 1: lo: <LOOPBACK,UP> mtu 16436 qdisc noqueue inet 127.0.0.1/8 scope host lo 2: eth0: <BROADCAST,MULTICAST,UP> mtu 1514 qdisc pfifo_fast qlen 1000 inet 10.10.20.100/32 scope global eth0 > ip route 127.0.0.0 dev lo scope link 10.10.20.0/24 dev eth0 scope link default via 10.10.20.1 dev eth0 - -- Now I add a route for my ha net: > ip route add 10.1...

...ht. Obviously I haven''t btu I cannot se where the error is. Can any here see my mistake(s)? $ Shorewall version: 2.0.12 $ ip addr show 1: lo: <LOOPBACK,UP> mtu 16436 qdisc noqueue link/loopback 00:00:00:00:00:00 brd 00:00:00:00:00:00 inet 127.0.0.1/8 brd 127.255.255.255 scope host lo 2: eth0: <BROADCAST,MULTICAST> mtu 1500 qdisc noop qlen 100 link/ether 00:0f:1f:64:44:4e brd ff:ff:ff:ff:ff:ff 3: eth1: <BROADCAST,MULTICAST,UP> mtu 1500 qdisc pfifo_fast qlen 100 link/ether 00:0f:1f:64:44:4f brd ff:ff:ff:ff:ff:ff inet 209.189.103.196/27 brd 209.189....

On 11/15/2014 12:08 AM, Tom Stellard wrote: > Can you send a plain-text version of this email. It's easier to read > and reply to. Sorry about that! Here's the plain text (I hope!): Hi all, OpenCL 2.0 introduced the notion of memory scope in atomic operations to global memory. These scopes are a hint to the underlying platform to optimize how synchronization is achieved. HSAIL also has a notion of memory scopes that is compatible with OpenCL 2.0. Currently, the LLVM IR uses a binary value (SingleThread/CrossThread) to represent...

...t;, isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, >> enums: !3, globals: !12) >> !2 = !DIFile(filename: "test", directory: ".") >> !3 = !{!4} >> !4 = !DICompositeType(tag: DW_TAG_enumeration_type, name: >> "GlobalLinkage", scope: !5, file: !5, line: 126, baseType: !6, size: 8, >> align: 8, elements: !7) >> !5 = !DIFile(filename: "builtin.zig", directory: >> "/home/andy/dev/zig/build/zig-cache") >> !6 = !DIBasicType(name: "u8", size: 8, encoding: DW_ATE_unsigned_char) &g...

...T256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 ISEL: Starting pattern match on root node: t9: ch = store<ST256[bitcast ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, t11, undef:i64 Skipped scope entry (due to false predicate) at index 14, continuing at 81 Skipped scope entry (due to false predicate) at index 82, continuing at 149 Skipped scope entry (due to false predicate) at index 150, continuing at 217 Skipped scope entry (due to false predicate) at index 218, continuing at 267...

...p metadata when that happens. Now I'm worried that this is not true. Here's a simple example: entry: %x1 = load %ptr1 // loading from ptr here to make all subsequent loads of %ptr safe to speculate %x2 = load %ptr2 ... somewhere: ... call i_may_throw() %y = load %ptr1, !alias.scope !{ !s1 } ... %z = store %ptr2, !alias.scope !{ !s1 }, !noalias !{ !s1 } So now some well-meaning pass swaps the order of the call and the load (legal because it is legal to speculate the load): somewhere: ... %y = load %ptr1, !alias.scope !{ !s1 } call i_may_throw() ... %z = store %...

...1, undef:i64 >>>> >>>> ISEL: Starting pattern match on root node: t9: ch = store<ST256[bitcast >>>> ([65 x i32]* @c to <64 x i32>*)](align=16)(tbaa=<0x3817578>)> t8, t7, >>>> t11, undef:i64 >>>> >>>> Skipped scope entry (due to false predicate) at index 14, continuing >>>> at 81 >>>> Skipped scope entry (due to false predicate) at index 82, continuing >>>> at 149 >>>> Skipped scope entry (due to false predicate) at index 150, continuing >>>> at...

Hi all, Currently, the LLVM IR uses a binary value (SingleThread/CrossThread) to represent synchronization scope on atomic instructions. We would like to enhance the representation of memory scopes in LLVM IR to allow more values than just the current two. The intention of this email is to invite comments on our proposal. There are some discussion before and it can be found here: https://groups.google.com/fo...

Hi Sameer, > On Jan 5, 2015, at 4:51 AM, Sahasrabuddhe, Sameer <Sameer.Sahasrabuddhe at amd.com> wrote: > > Right. The second version of my patches fixes the bitcode encoding. But now I see another potential problem with future bitcode if we require an ordering on the scopes. What happens when a backend later introduces a new scope that goes into the middle of the order? If they renumber the scopes to accomodate this, then existing bitcode for that backend will no longer work. The bitcode reader/writer cannot compensate for this since the values are backend-specific....

Hi All,   I have question regarding lexical scope information.   If I have .c source with scope as below. void func() {    //-- some code here..    { //parent scope       if() //high pass       {          int i;          for( i =0; i < FRAM_I; i++)          {          }       }       if() //low pass       {          int i;          for( i =0;...

Greetings, I have a Zig implementation of ceil which is emitted into LLVM IR like this: ; Function Attrs: nobuiltin nounwind define internal fastcc float @ceil(float) unnamed_addr #3 !dbg !644 { Entry: %x = alloca float, align 4 store float %0, float* %x call void @llvm.dbg.declare(metadata float* %x, metadata !649, metadata !494), !dbg !651 %1 = load float, float* %x, !dbg !652 %2 =