search for: schedwriter

Hi, I am having some trouble understanding the scheduling scheme for the C-A9. Looking at the ARMScheduleA9.td file I find this line that overrides the target SchedWrite with processor specific latencies. def : SchedAlias<WriteALU, A9WriteALU>; However, in this same file, I find the lines presented below, which are mapping the SchedReadWrite to, for example, the ANDri instruction. //

I'm trying to create a simplified 2 slot VLIW from an OR1K. The codebase I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've created an initial MyTargetSchedule.td def MyTargetModel : SchedMachineModel { // HW can decode 2 instructions per cycle. let IssueWidth = 2; let LoadLatency = 4; let MispredictPenalty = 16; // This flag is set to allow the

On Jul 22, 2013, at 11:50 AM, Tom Stellard <tom at stellard.net> wrote: > Hi, > > I'm working on defining a SchedMachineModel for the Southern Islands > family of GPUs, and I have two questions related to the > MachineScheduler. > > 1. I have a resource that can process 15 instructions at the same time. > In the TableGen definitions, should I do: > > def

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has

...o work with my ARCH. It is about the scheduler info which describes reading my ARCH's vector register. There are different latencies since forwarding/bypass appears. I give it as below example: def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } ... def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } ... Here I defined 3 different Writes with same latency number. Below shows the forwarding. def : ReadAdvance<MyReadVector, 5, [WriteVector]>; def : ReadAdvance<MyRead...

Thanks for prompt response, Andy This will work for cases when address is not modified. However this doesn’t seem to work for pre/post increment load stores. Consider data to address forwarding: $x0 = ldr x0, [x1] $x0, $x2 = ldr x2, [x0, 16]! The second instruction will have it’s own latency for address modification ($x0 register). So I don’t see how we can use ReadAdr stuff here. May be

Hi Andy, I'm working on defining new machine model for my target, But I don't understand how to define the in-order machine (reservation tables) in new model. For example, if target has IF ID EX WB stages should I do: let BufferSize=0 in { def IF: ProcResource<1>; def ID: ProcResource<1>; def EX: ProcResource<1>; def WB: ProcResource<1>; } def :

...bout the scheduler info which describes reading my ARCH's vector > register. There are different latencies since forwarding/bypass appears. I > give it as below example: > > def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } > ... > def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } > def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } > ... > > Here I defined 3 different Writes with same latency number. Below shows > the forwarding. > > def : ReadAdvance<MyReadVector, 5, [WriteVector]...

...which describes reading my ARCH's vector >> register. There are different latencies since forwarding/bypass appears. I >> give it as below example: >> >> def : WriteRes<WriteVector, [MyArchVALU]> { let Latency = 6; } >> ... >> def MyWriteAddVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } >> def MyWriteMulVector : SchedWriteRes<[MyArchVALU]> { let Latency = 6; } >> ... >> >> Here I defined 3 different Writes with same latency number. Below shows >> the forwarding. >> >> def : ReadAdvance<My...

On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine model. > it's make sense, but there is the another problem, the scheduled code is badly. > > load/store instruction always reuse the same register I filed PR17593 with this information. However, I

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =

...h pipeline independently. Some backend maintainers may still want to use itineraries if that level of precision is critical [1]. Another option is extending the new model. [2] I will assume that each queue is fully pipelined (4 ACQ ops can be in-flight). Forcing all this information into a single SchedWriteRes def would look like this: def P5600FLD : SchedWriteRes <[P5600UnitAGQ, P5600UnitFP]> { let Latency = 5; // 4 cycle load + 1 cycle FP writeback let NumMicroOps = 2; } This is bad (for an in-order processor) because it prevents FPLoad + FPx from being scheduled in the same cycle and fai...