search for: schedwrites

...iBITsr, and, 1>; In my mind, we have latencies defined from the ProcessorItineraries, latencies defined in the SchedReadWrite representation which are mapped through SchedAlias to the ANDri and, in the end, a mapping (or overriding?) of the latencies in the Itineraries by the processor-specific SchedWrites, through the InstRW? Can someone share some light on what scheduling/lantecy information is being used in this case? I cannot get my head around this... What am I missing here? Note: I also do not understand why use instregex if we could use the IIC_* for the InstRW. Thanks. - Tiago -----------...

I'm trying to create a simplified 2 slot VLIW from an OR1K. The codebase I'm working with is here <https://github.com/openrisc/llvm-or1k>. I've created an initial MyTargetSchedule.td def MyTargetModel : SchedMachineModel { // HW can decode 2 instructions per cycle. let IssueWidth = 2; let LoadLatency = 4; let MispredictPenalty = 16; // This flag is set to allow the

On Jul 22, 2013, at 11:50 AM, Tom Stellard <tom at stellard.net> wrote: > Hi, > > I'm working on defining a SchedMachineModel for the Southern Islands > family of GPUs, and I have two questions related to the > MachineScheduler. > > 1. I have a resource that can process 15 instructions at the same time. > In the TableGen definitions, should I do: > > def

Hi, I'm working on defining a SchedMachineModel for the Southern Islands family of GPUs, and I have two questions related to the MachineScheduler. 1. I have a resource that can process 15 instructions at the same time. In the TableGen definitions, should I do: def HWVMEM : ProcResource<15>; or let BufferSize = 15 in { def HWVMEM : ProcResource<1>; } 2. Southern Islands has

...ml#92849> [ author ] <http://lists.llvm.org/pipermail/llvm-dev/2015-November/author.html#92849> ------------------------------ Hi all, I am working on a backend that uses the ProcResource scheduling model and one limitation I found is that while it is possible to specify multiple SchedWrites in a ReadAdvance record, each write uses the same cycle count. I tried writing multiple ReadAdvance records for the same SchedRead, but tablegen does not seem to allow that. It would be useful to have a per-write cycle count to model different pipeline bypasses, where the cycle count depends on th...

Thanks for prompt response, Andy This will work for cases when address is not modified. However this doesn’t seem to work for pre/post increment load stores. Consider data to address forwarding: $x0 = ldr x0, [x1] $x0, $x2 = ldr x2, [x0, 16]! The second instruction will have it’s own latency for address modification ($x0 register). So I don’t see how we can use ReadAdr stuff here. May be

Hi Andy, I'm working on defining new machine model for my target, But I don't understand how to define the in-order machine (reservation tables) in new model. For example, if target has IF ID EX WB stages should I do: let BufferSize=0 in { def IF: ProcResource<1>; def ID: ProcResource<1>; def EX: ProcResource<1>; def WB: ProcResource<1>; } def :

...tp://lists.llvm.org/pipermail/llvm-dev/2015-November/author.html#92849> > > ------------------------------ > > Hi all, > > I am working on a backend that uses the ProcResource scheduling model > and one limitation I found is that while it is possible to specify > multiple SchedWrites in a ReadAdvance record, each write uses the same > cycle count. I tried writing multiple ReadAdvance records for the same > SchedRead, but tablegen does not seem to allow that. > > It would be useful to have a per-write cycle count to model different > pipeline bypasses, where the c...

...vm-dev/2015-November/author.html#92849> >> >> ------------------------------ >> >> Hi all, >> >> I am working on a backend that uses the ProcResource scheduling model >> and one limitation I found is that while it is possible to specify >> multiple SchedWrites in a ReadAdvance record, each write uses the same >> cycle count. I tried writing multiple ReadAdvance records for the same >> SchedRead, but tablegen does not seem to allow that. >> >> It would be useful to have a per-write cycle count to model different >> pipeline b...

On Oct 15, 2013, at 9:28 PM, Zakk <zakk0610 at gmail.com> wrote: > Hi Andy, thanks for your help!! > The scheduled code by method A is same as B when using the new machine model. > it's make sense, but there is the another problem, the scheduled code is badly. > > load/store instruction always reuse the same register I filed PR17593 with this information. However, I

Hi Andy, thanks for your help!! The scheduled code by method A is same as B when using the new machine model. it's make sense, but there is the another problem, the scheduled code is badly. load/store instruction always reuse the same register Source: #define N 2000000 static double b[N], c[N]; void Scale () { double scalar = 3.0; for (int j=0;j<N;j++) b[j] =

From: Andrew Trick [mailto:atrick at apple.com] Sent: 24 January 2014 21:52 To: Daniel Sanders Cc: LLVM Developers Mailing List (llvmdev at cs.uiuc.edu) Subject: Re: New machine model questions On Jan 24, 2014, at 2:21 AM, Daniel Sanders <Daniel.Sanders at imgtec.com<mailto:Daniel.Sanders at imgtec.com>> wrote: Hi Andrew, I seem to be making good progress on the P5600 scheduler