search for: schedulehazardrecogn

Is there any specific documentation on this? Is there a point of contact for this file that I might bug? So I have an instruction that needs noops inserted and it appears that the noops are being inserted in the EmitSchedule function of the PostRAScheduler. From the loop in EmitSchedule it looks like it's inserting noops whenever SUnit is NULL. I don't see anything in the DAG that appears

...ycle. Do you bundle those in the same group? What about register output dependencies? They can result from dead register defs. You may need to add your own checks to determine valid instruction groups. For example, you may not want to allow any DAG dependencies at all within the group. If the basic ScheduleHazardRecognizer is insufficient, you could try the approach that the Hexagon target uses. One of the engineers who works on that backend should be able to explain it better. -Andy

Hi all, I have a question regarding the latency of the true dependency of a store followed by an aliased load in ScheduleDAGInstrs. The latency seems to depend on the store and load being volatile or not as can be seen in the post-RA-sched debug output of the attached ARM example: $ llc -O3 -debug-only=post-RA-sched store_load_latency_test.ll ... SU(2): STRi12 %R2<kill>,

...he main difference between the PowerPC scheme > and a VLIW scheme, is that the CPU itself can form groups internally, > it is just more efficient if the groups are provided pre-made. Maybe > this difference, if it is one, is insignificant. Hal, I think you're asking whether to use the ScheduleHazardRecognizer or DFAPacketizer. I suggest sticking with the hazard recognizer unless you have an important problem that can't be solved that way. It's the API used by most targets and doesn't require a custom scheduler. Although I don't want to stop you from generalizing the DFA work either i...

...neraries. Regarding the Stalls argument to my method [Target]DispatchGroupSBHazardRecognizer::getHazardType() I always get the argument Stalls = 0. This is no surprise since in PostRASchedulerList.cpp we have only one call to it, in method SchedulePostRATDList::ListScheduleTopDown(): ScheduleHazardRecognizer::HazardType HT = HazardRec->getHazardType(CurSUnit, 0/*no stalls*/); Let me state what I have added to my back end to enable scheduling with hazards: - inspiring from lib/Target/PowerPC/PPCHazardRecognizers.h, I have created a class [Target]DispatchGroupSBHazardRecogni...

I'm considering writing more-detailed itineraries for some PowerPC CPUs that use the 'traditional' instruction grouping scheme. In essence, this means that multiple instructions will stall in some pipeline stage until a complete group is formed, then all will continue. I expect to provide CPU-specific code to help determine when the currently-waiting instructions would form a group.

Hi, I'm writing a backend for a proprietary microcontroller. I'm facing a limitation related to Live Interval Analysis. Some FPU instructions, most notably the FDIV, requires a few cycles to complete. There is a pipeline and, during the execution of the FDIV, others instructions could be executed in parallel, provided they don't use the same registers. This pipeline has been modeled

...PowerPC > > scheme and a VLIW scheme, is that the CPU itself can form groups > > internally, it is just more efficient if the groups are provided > > pre-made. Maybe this difference, if it is one, is insignificant. > > Hal, I think you're asking whether to use the > ScheduleHazardRecognizer or DFAPacketizer. I suggest sticking with > the hazard recognizer unless you have an important problem that can't > be solved that way. It's the API used by most targets and doesn't > require a custom scheduler. Although I don't want to stop you from > generalizing t...

Hello. I am progressing a bit with difficulty with the post RA scheduler (PostRASchedulerList.cpp with ScoreboardHazardRecognizer) - the problem I have is that it doesn't advance at the next available instruction when the overridden ScoreboardHazardRecognizer::getHazardType() method returns NoopHazard and it gets stuck at the same instruction (store in my runs). Just to make sure:

...en/RegisterCoalescer.h -- Installing: /usr/local/llvm-2.8/include/llvm/CodeGen/RegisterScavenging.h -- Installing: /usr/local/llvm-2.8/include/llvm/CodeGen/RuntimeLibcalls.h -- Installing: /usr/local/llvm-2.8/include/llvm/CodeGen/ScheduleDAG.h -- Installing: /usr/local/llvm-2.8/include/llvm/CodeGen/ScheduleHazardRecognizer.h -- Installing: /usr/local/llvm-2.8/include/llvm/CodeGen/SchedulerRegistry.h -- Installing: /usr/local/llvm-2.8/include/llvm/CodeGen/SelectionDAG.h -- Installing: /usr/local/llvm-2.8/include/llvm/CodeGen/SelectionDAGISel.h -- Installing: /usr/local/llvm-2.8/include/llvm/CodeGen/SelectionDAGNod...

On Thu, Sep 30, 2010 at 3:08 PM, Samuel Williams <space.ship.traveller at gmail.com> wrote: > Hi, > > I might just be doing something stupid, but when I do > > $ cmake -DCMAKE_INSTALL_PREFIX=/usr/local/llvm-2.8 -DCMAKE_BUILD_TYPE=Release .. > $ sudo make install > > I don't get the expected headers in >        /usr/local/llvm-2.8/include/llvm > > It is

Hi, I might just be doing something stupid, but when I do $ cmake -DCMAKE_INSTALL_PREFIX=/usr/local/llvm-2.8 -DCMAKE_BUILD_TYPE=Release .. $ sudo make install I don't get the expected headers in /usr/local/llvm-2.8/include/llvm It is simply an empty directory. What am I doing wrong? This is on Mac OS X, CMake 2.8+ Kind regards, Samuel

...;> +#include "llvm/CodeGen/MachineFrameInfo.h" >> +#include "llvm/CodeGen/MachineInstrBuilder.h" >> +#include "llvm/CodeGen/MachineRegisterInfo.h" >> +#include "llvm/CodeGen/MachineFunctionAnalysis.h" >> +#include "llvm/CodeGen/ScheduleHazardRecognizer.h" >> +#include "llvm/Target/TargetMachine.h" >> +#include "llvm/Target/TargetInstrInfo.h" >> +#include "llvm/Target/TargetRegisterInfo.h" >> +#include "llvm/ADT/DenseMap.h" >> +#include "llvm/ADT/Statistic.h"...