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0x0f 0x6f 0xc8 And 0x0f 0x7f 0xc1 Should both be movq % mm0, % mm1. (AT&T) However, llvm 3.4 at least does not recognise the second variant as being a valid instruction. We are currently compiling up latest src incase it has been fixed. If not, could someone take a look or recommend how to fix? Lee -------------- next part -------------- An HTML attachment was scrubbed... URL:

Hi, This patch fixes outs/ins of MOV16mr instruction of X86. Thanks. diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index e9a0431..f5b2064 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; -def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src),...

Hello, Here is one question regarding the LLVM TableGen: Which file in the llvm/lib/Target/X86 folder describes how the bits in the EFLAGS register are modified by the x86 instructions? For example, in the "X86InstrInfo.td" file, lines 2134-2135, it says: let SchedRW = [WriteALU], Defs = [EFLAGS], Uses = [EFLAGS] in { def CLC : I<0xF8, RawFrm, (outs), (ins), "clc", []>; So it says the Defs of CLC is EFLAGS, but actually the CLC instruction only clears the "CF" flag in the EFLAGS register and has nothing to do with the other bits of...

Here's a couple examples for mapping an intrinsic to an X86 instruction from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can find others. let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], IIC_SSE_PREFETCH>, PD; let Predicates = [HasCLWB], SchedRW = [WriteLoad] in def CLWB : I<0xAE, MRM6m, (out...

...18, 2018 at 7:43 PM, Craig Topper <craig.topper at gmail.com> wrote: > Here's a couple examples for mapping an intrinsic to an X86 instruction > from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can > find others. > > let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in > def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), > "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], > IIC_SSE_PREFETCH>, PD; > > let Predicates = [HasCLWB], SchedRW = [WriteLoad] in > def CLWB...

Hello all. LLVM newbie here. If anything seems glaringly wrong with my use of LLVM, that's probably why. Here's what I'm trying to do. I have modified the gem5 simulator to accept a "new" x86 instruction. I've done this by just reserving the opcode in gem5's ISA specification, just as all other instructions are specified. I'm trying to get an LLVM backend to

...pper <craig.topper at gmail.com> > wrote: > >> Here's a couple examples for mapping an intrinsic to an X86 instruction >> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can >> find others. >> >> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in >> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), >> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], >> IIC_SSE_PREFETCH>, PD; >> >> let Predicates = [HasCLWB], SchedRW = [WriteLoad...

...il.com> >> wrote: >> >>> Here's a couple examples for mapping an intrinsic to an X86 instruction >>> from X86InstrInfo.td. If you look for int_x86_* in any X86Instr*.td you can >>> find others. >>> >>> let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in >>> def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src), >>> "clflushopt\t$src", [(int_x86_clflushopt addr:$src)], >>> IIC_SSE_PREFETCH>, PD; >>> >>> let Predicates = [HasCLWB],...

...> > Thanks. > > > > > > diff --git a/lib/Target/X86/X86InstrInfo.td > b/lib/Target/X86/X86InstrInfo.td > > index e9a0431..f5b2064 100644 > > --- a/lib/Target/X86/X86InstrInfo.td > > +++ b/lib/Target/X86/X86InstrInfo.td > > @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in { > > def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), > > "mov{b}\t{$src, $dst|$dst, $src}", > > [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; > > -def MOV16mr : I<0x89, MRMDestMem...

From: Andrew Trick [mailto:atrick at apple.com] Sent: 24 January 2014 21:52 To: Daniel Sanders Cc: LLVM Developers Mailing List (llvmdev at cs.uiuc.edu) Subject: Re: New machine model questions On Jan 24, 2014, at 2:21 AM, Daniel Sanders <Daniel.Sanders at imgtec.com<mailto:Daniel.Sanders at imgtec.com>> wrote: Hi Andrew, I seem to be making good progress on the P5600 scheduler

Hello Andy, Thank you for your offer to work together on implementing the your new scheduler on X86. I can start working on this right away. In case you were unaware, the new Silvermont micro-architecture is only out of order on the integer side. The SSE instructions are still in order, so the current postRA scheduler is very beneficial for code with lots of SSE instructions, such as the ISPC