Displaying 3 results from an estimated 3 matches for "schedling".
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2018 May 09
1
Is there any relationship between IR instruction and execution time
Hi Yin,
MCA does support the –mcpu and –mtriple options. We have one arm test in llvm/test/tools/llvm-mca/ARM for a cortex-9, which is an Out of Order chip.
Hope that helps!
-Matt
From: Yin Liu <yinliu.tiger at gmail.com>
Sent: Tuesday, May 8, 2018 2:49 PM
To: Davis, Matthew <Matthew.Davis at sony.com>
Cc: llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] Is there any relationship
2014 Sep 18
6
[PATCH v2 2/3] hw_random: fix stuck in catting hwrng attributes
Amos Kong <akong at redhat.com> writes:
> I started a QEMU (non-smp) guest with one virtio-rng device, and read
> random data from /dev/hwrng by dd:
>
> # dd if=/dev/hwrng of=/dev/null &
>
> In the same time, if I check hwrng attributes from sysfs by cat:
>
> # cat /sys/class/misc/hw_random/rng_*
>
> The cat process always gets stuck with slow backend (5
2014 Sep 18
6
[PATCH v2 2/3] hw_random: fix stuck in catting hwrng attributes
Amos Kong <akong at redhat.com> writes:
> I started a QEMU (non-smp) guest with one virtio-rng device, and read
> random data from /dev/hwrng by dd:
>
> # dd if=/dev/hwrng of=/dev/null &
>
> In the same time, if I check hwrng attributes from sysfs by cat:
>
> # cat /sys/class/misc/hw_random/rng_*
>
> The cat process always gets stuck with slow backend (5