search for: sbb

Hi, I have the x86 SBB instruction. how should I represent this in LLVM IR. (as part of a decompiler from binary to LLVM IR) Pre-conditions: %eax = 0xffffffff %edx = 0xffffffff %carry = 1 SBB %eax, %edx // %edx is the destination doing %edx = %edx - (%eax + carry) JC jump_destination1 // If the Carry flag is...

Look at the __builtin_addc* builtins in clang. I am currently working on an optimization which transforms said intrinsics into chains of ADCs/SBBs. Michael On Jun 28, 2013, at 5:51 AM, James Courtier-Dutton <james.dutton at gmail.com> wrote: > Hi, > > I have the x86 SBB instruction. how should I represent this in LLVM > IR. (as part of a decompiler from binary to LLVM IR) > > Pre-conditions: > %eax = 0xffffff...

...if (value < 1) ret = 0x40; else ret = 0x61; return ret; } It compiles with GCC -O2 to (rather cleverly removing any branches): 0000000000000000 <test61>: 0: 83 ff 01 cmp $0x1,%edi 3: 19 c0 sbb %eax,%eax 5: 83 e0 df and $0xffffffdf,%eax 8: 83 c0 61 add $0x61,%eax b: c3 retq How would I represent the SBB instruction in LLVM IR? Would I have to first convert the ASM to something like: 0000000000000000 <test61&...

...[pbx_config] 2. Goto(s|2) [pbx_config] 's' => 1. Answer() [pbx_config] 2. Set(CALLERID(all)=${CALLERID(all)}) [pbx_config] 3. Background(sbb-greets) [pbx_config] 4. Goto(s|1) [pbx_config] 't' => 1. Goto(s|1) [pbx_config] =============================================================================== i...

...ecx, -8 mov eax, edx .LBB0_3: # Parent Loop BB0_2 Depth=1 | # 4 instructions instead of 6, r8 not clobbered! lea r8d, [rax + rax] | add eax, eax mov edx, r8d | # CF is set from the MSB of EAX xor edx, -306674912 | sbb edx, edx test eax, eax | # EDX is 0xFFFFFFFF if CF set, else 0 mov eax, edx | and edx, -306674912 cmovns eax, r8d | xor eax, edx add ecx, 1 jne .LBB0_3 jmp .LBB0_4 .LBB0_5:...

It might sound stupid, but I'd like to know if there's any difference. Are those 3 line the same? WITH_KMS=YES WITH_KMS="YES" WITH_KMS=yes Best regards Zoran

"Sanjay Patel" <spatel at rotateright.com> wrote: > IIUC, you want to use x86-specific bit-hacks (sbb masking) in cases like > this: > unsigned int foo(unsigned int crc) { > if (crc & 0x80000000) > crc <<= 1, crc ^= 0xEDB88320; > else > crc <<= 1; > return crc; > } To document this for x86 too: rewrite the function slightly unsigned int f...

...= 0x40; > else > ret = 0x61; > return ret; > } > > It compiles with GCC -O2 to (rather cleverly removing any branches): > 0000000000000000 <test61>: > 0: 83 ff 01 cmp $0x1,%edi > 3: 19 c0 sbb %eax,%eax > 5: 83 e0 df and $0xffffffdf,%eax > 8: 83 c0 61 add $0x61,%eax > b: c3 retq > > How would I represent the SBB instruction in LLVM IR? > Would I have to first convert the ASM to something like: &g...

...eax, edx ret | ret llsign: # @llsign xor ecx, ecx | xor edx, edx mov eax, dword ptr [esp + 8] | mov eax, dword ptr [esp + 8] cmp ecx, dword ptr [esp + 4] | cmp edx, dword ptr [esp + 4] sbb ecx, eax | sbb edx, eax setl cl | cdq sar eax, 31 | setl al movzx ecx, cl | movzx eax, al add eax, ecx | add eax, edx mov edx,...

I followed the manual and got 3 problems 1. When i start samba i got error: ../dsdb/dns/dns_update.c:249: Failed DNS update - NT_STATUS_IO_TIMEOUT 2. When i join some computer bind9 doesent update the host in DNS. 3. When i start command /usr/local/samba/sbin/samba_dnsupdate --verbose shell sometimes back result sometimes not.'' -- -- Pozdrav Aleksandar

Greetings. I am planning on getting my RHCE in the near future. I thinking I should wait until 6 comes out before proceeding. That being said, I don't want to wait past the end of this year. That being said, do you all have any information about how long it takes for their training platform to catch up to their release? Which is to say, if RHES 6 is released on day 1, at what point

We''re utilizing the Dashboard to manage which modules are included for each node. In this setup, nodes.pp is empty. E.g.: modules/repos includes the various repository files for each OS. ...And in the dashboard, there is a class titled ''repos'' and is assigned to the various nodes that we want to have their repo files managed. I''d like the

...ile("btrl %1,%0" : ADDR : "Ir" (nr)); } /* @@ -198,7 +198,7 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr) { int oldbit; - asm volatile(LOCK_PREFIX "bts %2,%1\n\t" + asm volatile(LOCK_PREFIX "btsl %2,%1\n\t" "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); return oldbit; @@ -230,7 +230,7 @@ static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) { int oldbit; - asm("bts %2,%1\n\t" + asm("btsl %2,%1\n\t" "...

Hello Mailing List I got a severe network error message at a HP DL360 Server. The kernel log says: ----------------------------------- /var/log/messages ----------------------------------------------------------------- Mar 19 15:45:06 server kernel: do_IRQ: 2.168 No irq handler for vector (irq -1) Mar 19 15:45:17 server kernel: bnx2 0000:02:00.1: eth1: DEBUG: intr_sem[0] PCI_CMD[00100446] Mar 19

...ret = 0x61; >> return ret; >> } >> >> It compiles with GCC -O2 to (rather cleverly removing any branches): >> 0000000000000000 <test61>: >> 0: 83 ff 01 cmp $0x1,%edi >> 3: 19 c0 sbb %eax,%eax >> 5: 83 e0 df and $0xffffffdf,%eax >> 8: 83 c0 61 add $0x61,%eax >> b: c3 retq >> >> How would I represent the SBB instruction in LLVM IR? >> Would I have to first convert th...

...be desirable to add primitives for retrieving both the low and high half of a multiplication and optimisations to combine where wide multiplications are available on the chip? c) I want to ask something about retrieving the carry or borrow from an addition or subtraction and using it in an ADC or SBB..... not sure what to ask..... d) Are you guys at all interested in supporting languages that provide multiprecision arithmetic? I have a vague notion that I'd like to sign on to help with that (and may be able to bring some other experienced devels with me if there was some interest). I did...

...(nr)); > } > > /* > @@ -198,7 +198,7 @@ static inline int test_and_set_bit(int nr, volatile unsigned long *addr) > { > int oldbit; > > - asm volatile(LOCK_PREFIX "bts %2,%1\n\t" > + asm volatile(LOCK_PREFIX "btsl %2,%1\n\t" > "sbb %0,%0" : "=r" (oldbit), ADDR : "Ir" (nr) : "memory"); > > return oldbit; > @@ -230,7 +230,7 @@ static inline int __test_and_set_bit(int nr, volatile unsigned long *addr) > { > int oldbit; > > - asm("bts %2,%1\n\t" > + asm...

...quest that the bug database is used instead. > > On Tue, Nov 27, 2018 at 4:37 PM Stefan Kanthak <stefan.kanthak at nexgo.de> > wrote: > >> "Sanjay Patel" <spatel at rotateright.com> wrote: >> >> > IIUC, you want to use x86-specific bit-hacks (sbb masking) in cases like >> > this: >> > unsigned int foo(unsigned int crc) { >> > if (crc & 0x80000000) >> > crc <<= 1, crc ^= 0xEDB88320; >> > else >> > crc <<= 1; >> > return crc; >> > } >...

...ere appear to be CALL32r instructions that also call locations outside the program. Is there any way to determine the location of the call target more precisely? I tried for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(), SE = BB->succ_end(); SI != SE; ++SI) { MachineBasicBlock *SBB = *SI; if (SBB->getParent()->getFunction()->isDeclaration()) skip = true; } but it seems not to do what I intended. -- View this message in context: http://www.nabble.com/How-to-differentiate-between-external-and-internal-calls-in-llc--tp25316545p25316545.html Sent from the LLVM - De...

On 3/12/2013 11:20 AM, James Courtier-Dutton wrote: > It compiles with GCC -O2 to (rather cleverly removing any branches): > 0000000000000000 <test61>: > 0: 83 ff 01 cmp $0x1,%edi > 3: 19 c0 sbb %eax,%eax > 5: 83 e0 df and $0xffffffdf,%eax > 8: 83 c0 61 add $0x61,%eax > b: c3 retq > > How would I represent the SBB instruction in LLVM IR? If you're decompiling an assembly language into IR, it i...