Displaying 20 results from an estimated 4597 matches for "bb".
2018 Apr 09
2
How to get the case value from Machine Instruction
...et esasly.
but it seems no case -value in Machine Instruction.
The MI as follows:
Frame Objects:
fi#0: size=1, align=0, at location [SP]
fi#1: size=4, align=4, at location [SP+8]
fi#2: size=4, align=4, at location [SP+4]
fi#3: size=4, align=4, at location [SP]
Jump Tables:
%jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5
%bb.0: derived from LLVM BB %0
%r0 = MOVi 0, 14, %noreg, %noreg
STRi12 %r0, %stack.1, 14, %noreg
%r0 = MOVi 4, 14, %noreg, %noreg
STRi12 %r0, %stack.2, 14, %noreg
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = SUBri %r0, 1, 14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implicit-def %c...
2013 Apr 10
3
[LLVMdev] If Conversion and predicated returns
Evan, et al.,
I've come across a small issue when using the if conversion pass in PPC to generate conditional returns. Here's a small example:
** Before if conversion **
BB#0: derived from LLVM BB %entry
%R3<def> = LI 0
%CR0<def> = CMPLWI %R3, 0
BCC 68, %CR0, <BB#3>
Successors according to CFG: BB#3(16) BB#1(16)
BB#1: derived from LLVM BB %while.body.lr.ph
Live Ins: %R3
Predecessors according to CFG: BB#0...
2017 Jul 28
2
Tail merging "undef" with a defined register: wrong code
I've looked into that and it's not going to be simple, unfortunately.
Here's the original example again:
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.2
J2_jumpt undef %p0, %bb.2, implicit-def %pc
J2_jump %bb.1, implicit-def %pc
bb.1:
successors: %bb.3
%r0 = L2_loadruh_io undef %r0, 0
PS_storerhabs 0, killed %r0
J2_jump %bb.3, implicit-def %pc
bb.2:
successors: %b...
2009 Jan 30
4
modules not processing in order
...ar/lib/puppet/localconfig.yaml
notice: Starting catalog run
notice: //Node[puppetslave.example.org]/defaultnode/shared-default/
homedirectories/Exec[/bin/tar xzf /tmp/ipswich.tar.gz]/returns:
executed successfully
err: //Node[puppetslave.example.org]/defaultnode/shared-default/
bigbrother/File[/var/bb/bbc1.9e-btf_linux/bin]/ensure: change from
absent to file failed: Could not set file on ensure: No such file or
directory - /var/bb/bbc1.9e-btf_linux/bin.puppettmp at /var/lib/puppet/
modules/bigbrother/manifests/init.pp:79
warning: //Node[puppetslave.example.org]/defaultnode/shared-default/
bigbro...
2018 May 16
0
Bug in TailDuplicator?
Hi,
I think there might be a bug in the tail duplicator (called from
MachineBlockPlacement in my case), when duplicating a block that
contains an implicit fall-through.
Suppose you have the following blocks
BB#1:
Predecessors according to CFG: BB#2
...
conditional_branch <BB#3>
< implicit fall-through to BB#2 >
Successors according to CFG: BB#2 BB#3
BB#2:
Predecessors according to CFG: BB#1 BB#0
...
unconditional_branch <BB#1>
Successors according to C...
2006 Dec 04
2
[LLVMdev] problem using scc_iterator on CallGraph
...------------------------------
; ModuleID = 'bugpoint-reduced-simplified.bc'
target datalayout = "e-p:32:32"
target endian = little
target pointersize = 32
target triple = "i686-pc-linux-gnu"
implementation ; Functions:
void %execute() {
entry:
br bool false, label %bb688, label %cond_true
cond_true: ; preds = %entry
ret void
bb: ; preds = %bb688
switch int 0, label %bb684 [
int 33, label %bb412
int 35, label %bb604
int 37, label %bb531
int 38, label %bb418
int 42, label %bb495
int 43, label %bb467
int 45, label %cond_true484
int 47,...
2012 Jun 13
2
[LLVMdev] Assert in live update from MI scheduler.
...at codeaurora.org> wrote:
> Andy,
>
> You are probably right here β look at this β before phi elimination this code looks much more sane:
>
> # *** IR Dump After Live Variable Analysis ***:
> # Machine code for function push: SSA
> Function Live Outs: %R0
>
> BB#0: derived from LLVM BB %entry
> %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5
> %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
> Successors according to CFG: BB#1
>
> BB#1: derived from LLVM BB %for.cond
> Predecessors according to CFG: BB#0...
2017 Jul 27
2
Tail merging "undef" with a defined register: wrong code
...same as the original. At the same time, any subsequent optimization may
"exploit" the incorrect liveness information to do something bad. If
you add -run-pass if-converter, you'll get:
# After If Converter
# Machine code for function fred: IsSSA, NoPHIs, TracksLiveness, NoVRegs
BB#0:
%R0<def> = L2_ploadruhf_io %P0<undef>, %R0<undef>, 0, %R0<imp-use>
PS_storerhabs 0, %R0
PS_jmpret %R31<kill>, %PC<imp-def>
# End machine code for function fred.
*** Bad machine code: Using an undefined physical register ***
- funct...
2015 Apr 16
2
[LLVMdev] Multiple connected components in live interval
...e the condition.
I will therefore try to explain:
The options to llc are -optimize-regalloc -O0. The function is
meaningless - with -O3 it just returns zero.
It contains two nested loops, with a call inside the inner loop, which
is a CFG-diamond.
The PHI-nodes look like this in the inner loop:
BB#5: // Inner loop header
Predecessors according to CFG: BB#1 BB#4
vreg7<def> = PHI %vreg29, <BB#1>, %vreg4, <BB#4>
...
Successors according to CFG: BB#2 BB#6
BB#2:
Predecessors according to CFG: BB#5
...
Successors according to CFG: BB#3 BB#4
BB#3...
2018 Apr 09
0
How to get the case value from Machine Instruction
...y.
but it seems no case -value in Machine Instruction.
The MI as follows:
Frame Objects:
fi#0: size=1, align=0, at location [SP]
fi#1: size=4, align=4, at location [SP+8]
fi#2: size=4, align=4, at location [SP+4]
fi#3: size=4, align=4, at location [SP]
Jump Tables:
%jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5
%bb.0: derived from LLVM BB %0
%r0 = MOVi 0, 14, %noreg, %noreg
STRi12 %r0, %stack.1, 14, %noreg
%r0 = MOVi 4, 14, %noreg, %noreg
STRi12 %r0, %stack.2, 14, %noreg
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = SUBri %r0, 1, 14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implic...
2012 Jun 13
0
[LLVMdev] Assert in live update from MI scheduler.
...ack = xx_stack; stack; stack = stack->next)
top = stack;
yy_instr = top->first;
}
If the loop never iterates, "top" will have garbage in it. If it iterates
even once, it will presumably have valid pointer. Bad, but perfectly valid
code.
In SSA it looked like this:
BB#0: derived from LLVM BB %entry
%vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<Dummy def.
%vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
Successo...
2017 Jul 27
2
Tail merging "undef" with a defined register: wrong code
The comment in test/CodeGen/X86/branchfolding-undef.mir states that such
merging is legal, however doing so can actually generate wrong code:
Consider this (valid code):
---
name: fred
tracksRegLiveness: true
body: |
bb.0:
successors: %bb.1, %bb.2
J2_jumpt undef %p0, %bb.2, implicit-def %pc
J2_jump %bb.1, implicit-def %pc
bb.1:
successors: %bb.3
%r0 = L2_loadruh_io undef %r0, 0
PS_storerhabs 0, killed %r0
J2_jump %bb.3, implicit-def %pc
bb.2:
successors: %b...
2017 Jul 28
2
Tail merging "undef" with a defined register: wrong code
...rzysz at codeaurora.org> wrote:
>>
>> I've looked into that and it's not going to be simple, unfortunately.
>>
>> Here's the original example again:
>>
>> ---
>> name: fred
>> tracksRegLiveness: true
>>
>> body: |
>> bb.0:
>> successors: %bb.1, %bb.2
>> J2_jumpt undef %p0, %bb.2, implicit-def %pc
>> J2_jump %bb.1, implicit-def %pc
>>
>> bb.1:
>> successors: %bb.3
>> %r0 = L2_loadruh_io undef %r0, 0
>> PS_storerhabs 0, killed %r0
>...
2006 Dec 04
0
[LLVMdev] problem using scc_iterator on CallGraph
...;bugpoint-reduced-simplified.bc'
> target datalayout = "e-p:32:32"
> target endian = little
> target pointersize = 32
> target triple = "i686-pc-linux-gnu"
>
> implementation ; Functions:
>
> void %execute() {
> entry:
> br bool false, label %bb688, label %cond_true
>
> cond_true: ; preds = %entry
> ret void
>
> bb: ; preds = %bb688
> switch int 0, label %bb684 [
> int 33, label %bb412
> int 35, label %bb604
> int 37, label %bb531
> int 38, label %bb418
> int 42, label %bb495
> int...
2016 Mar 22
3
Instrumented BB in PGO
Hello,
I have a question regarding PGO instrumented BBs (I use IR-level
instrumentation).
It seems that instrumented BBs do not match between the two compilations
for profile-gen and profile-use for some cases. Here is an example from
SPECcpu 2006 lbm (a simple case consisting of just two modules).
In the first compilation, we have 5 instrumentation p...
2012 Jun 08
2
[LLVMdev] Strong vs. default phi elimination and single-reg classes
...s,
and the CTR register is allocated as it should be. When using the
default phi elimination, extra copies are introduced (which I don't
completely understand), and the register allocator tries to spill the
count register. For example, with strong-phi elimination, I get (as a
simple example):
BB#0: derived from LLVM BB %entry
Live Ins: %X3
%vreg2<def> = COPY %X3<kill>; G8RC:%vreg2
%vreg4<def> = LI 2048; GPRC:%vreg4
%vreg3<def> = OR8To4 %vreg2<kill>, %vreg2; GPRC:%vreg3 G8RC:%vreg2
%vreg9<def> = COPY %vreg4<kill>; GPRC:%vreg9,%vreg4
%vre...
2012 Jun 08
0
[LLVMdev] Strong vs. default phi elimination and single-reg classes
On Jun 7, 2012, at 7:31 PM, Hal Finkel wrote:
> 112B BB#1: derived from LLVM BB %for.body, ADDRESS TAKEN
> Predecessors according to CFG: BB#0 BB#1
> %vreg12<def> = PHI %vreg13, <BB#1>, %vreg11, <BB#0>;CTRRC8:%vreg12,%vreg13,%vreg11
> %vreg13<def> = COPY %vreg12<kill>; CTRRC8:%vreg13,%vreg12
> %vreg13...
2012 Jun 14
1
[LLVMdev] Assert in live update from MI scheduler.
...; stack = stack->next)
> top = stack;
> yy_instr = top->first;
> }
>
> If the loop never iterates, βtopβ will have garbage in it. If it iterates even once, it will presumably have valid pointer. Bad, but perfectly valid code.
>
> In SSA it looked like this:
> BB#0: derived from LLVM BB %entry
> %vreg5<def> = IMPLICIT_DEF; IntRegs:%vreg5 <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<Dummy def.
> %vreg4<def> = TFRI_V4 <ga:@xx_stack>; IntRegs:%vreg4
>...
2018 Apr 10
1
How to get the case value from Machine Instruction
...y.
but it seems no case -value in Machine Instruction.
The MI as follows:
Frame Objects:
fi#0: size=1, align=0, at location [SP]
fi#1: size=4, align=4, at location [SP+8]
fi#2: size=4, align=4, at location [SP+4]
fi#3: size=4, align=4, at location [SP]
Jump Tables:
%jump-table.0: %bb.2 %bb.3 %bb.4 %bb.5
%bb.0: derived from LLVM BB %0
%r0 = MOVi 0, 14, %noreg, %noreg
STRi12 %r0, %stack.1, 14, %noreg
%r0 = MOVi 4, 14, %noreg, %noreg
STRi12 %r0, %stack.2, 14, %noreg
%r0 = LDRi12 %stack.2, 14, %noreg
%r0 = SUBri %r0, 1, 14, %noreg, %noreg
CMPri %r0, 3, 14, %noreg, implic...
2006 Dec 04
1
[LLVMdev] problem using scc_iterator on CallGraph
...#39;
>>target datalayout = "e-p:32:32"
>>target endian = little
>>target pointersize = 32
>>target triple = "i686-pc-linux-gnu"
>>
>>implementation ; Functions:
>>
>>void %execute() {
>>entry:
>> br bool false, label %bb688, label %cond_true
>>
>>cond_true: ; preds = %entry
>> ret void
>>
>>bb: ; preds = %bb688
>> switch int 0, label %bb684 [
>> int 33, label %bb412
>> int 35, label %bb604
>> int 37, label %bb531
>> int 38, label %bb418
>>...