search for: s21

...example, in figure 2.1 at http://lmdvr.r-forge.r-project.org/figures/figures.html. In this case, I would like to combine the the top strip, since all three pictures in the same row have the same level based on the first strip. In other words, instead of | -- S11 -- | -- S11 -- | -- S11 -- | | -- S21 -- | -- S22 -- | -- S23 -- | I would like my graph to look like | ----------------- S11 ---------------- | | -- S21 -- | -- S22 -- | -- S23 -- | In there a way I can do it? Thanks! JD [[alternative HTML version deleted]]

Hello, I am trying to plot multiple histograms with the same scales, etc into one plot. The commands below produce a 3 page PDF with each histogram occupying the upper right quadrant. And use slightly different scales on the X and Y axes. > s21 <- dat[dat$sc_recov=="21",] > s21.ED <- subset(s21, select=(bbED)) > s31 <- all[all$sc_recov=="31",] > s31.ED <- subset(s31, select=(bbED)) > s41 <- all[all$sc_recov=="41",] > s41.ED <- subset(s41, select=(bbED)) > pdf("234_1_ED...

Hi Folks, Given k RVs with MVN distribution N(mu,S) (S a kxk covariance matrix), let (w.l.o.g.) X1 denote the first r of them, and X2 the last (k-r). Likewise, let mu1 and mu2 denote their respective expectations. Then, of course, the expectation of X2 given X1=x1 is mu2 + S21*inv(S22)*(x1 - mu1) and the covariance matrix of X2 given X1=x2 is S22 - S21*inv(X11)*S12 where Sij is the matrix derived from S by taking the rows corresponding to the indices of Xi and the columns corresponding to the indices of Xj, and these define the MVN conditional distribution of X2 giv...

Hi!   I want to print the output all together with a single column name   s21<-c(1:1000); var21<-lapply(s21,function(x){    ns<-rnorm(78,8,9);    n<-length(ns);    Mn<-mean(ns)    Sn2<-var(ns)    return(cbind(x,Mn,Sn2)); }); var21 but my code is giving me somewhat like the following [[1]] x   Mn          Sn2   [1,] 1 7.86 10.56540 [[2]] x   Mn          S...

Hi, I need construct box plot graph, but I want keep Groups order karla = data.frame( Groups = factor(rep(c('CPre','SPre','C7','S7','C14','S14','C21','S21'), 11)), Time = rep(c(0,7,14,21), 11), Resp = valor ) boxplot(Resp~Groups, order=T) doesn't work. How do this? -------------------------------------- Silvano Cesar da Costa Departamento de Estat?stica Universidade Estadual de Londrina Fone: 3371-4346

...LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...LDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp...

I experimented with floppy sizes. Eg. I used FDFORMAT v1.8 to format a Disk fdformat a: t82 s21 D10 (I even have a modified version of FDFORMAT that creates only 1 FAT to save space, but I'm not using that.) All the information is written nicely to the Boot-Record http://home.freeuk.com/foxy2k/disk/disk3.htm But SYSLINUX seems to ignore the information. While DOS boots fine from th...

Hi, I am trying to read the "credit.lisp" file of the Japanese credit database in UCI repository, but it is in lisp format which I do not know how to read. I have not found how to do that in the foreign library http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening <http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening> Could anyone help me? Best

...conditioning variable X1 (implies complementary set of ### columns of X for the variable X2 whose conditional ### distribution (X2 | X1=x1) is to be found). iX1<-ixX(S, ... ); iX2<-!iX1; s11<-solve(S[iX1,iX1,drop=FALSE]); s12<-S[iX1,iX2,drop=FALSE]; s21<-S[iX2,iX1,drop=FALSE]; s22<-S[iX2,iX2,drop=FALSE]; mu1<-mu[,iX1,drop=FALSE]; mu2<-mu[,iX2,drop=FALSE]; Cmu <- (x1%.+%(-mu1))%*%s11%*%s12 %.+% mu2; Cvar <- s22 - s21%*%s11%*%s12; list(Cmu=Cmu,Cvar=Cvar,iX1=iX1,iX2=iX2) } =================================================...

Dear Knowledgeable R Community Members, Please excuse my ignorance, I apologize in advance if this is an easy question, but I am a bit stumped and could use a little guidance. I have a finite mixture modeling problem -- for example, a 2-component Weibull mixture -- where the components have a large overlap, and I am trying to adapt the "mclust" package which concern to normal

I would like to call my own DID number from outside, get into voicemail, and then push '#' to exit into VoicemailMain. Is there a way to do this?

...question as stopping the merge to head, I'm just making sure I got it right... The rest looks correct. + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, Does this mean that for floating point support in GHC, you need VFP registers? I don't know much how tablegen would work in this case, but I'd expect it to break during codegen (with a horrid error message) if you try to compile that to an ARMv4-ish core. Maybe you ne...

...10 2 S16 17 s 1 7 4 5 1 6 3 5 S17 18 s 6 2 7 4 6 2 7 4 S18 19 s 9 4 8 5 10 4 6 3 S19 20 s 8 2 6 5 9 2 6 4 S20 21 s 6 5 5 7 6 6 5 5 S21 22 s 8 8 3 7 6 7 5 3 S22 23 s 11 4 6 7 1 1 6 4 S23 24 s 6 3 2 4 6 4 2 2 S24 25 s 4 4 6 6 2 3 4 6 S25 26 w 5 9 4 7 3 7 3 5 S26 27 w...

Hello, first of all: one of the LLVM 3.0 new feature was a support for GHC specific calling convention on ARM platform. It looks like this support was merged just into 3.0 branch, specifically it appeared in 3.0 RC2. Anyway, I hope this is just a mistake or omission that such support was merged only into 3.0 and not also into HEAD. I've just found it by testing LLVM 3.1 with GHC 7.4.2 and

The stripe and stride options do two things: - shift block and inode bitmaps in each group to be on different disks - align the block allocation to the stripe and stride boundaries to avoid read-modify-write in RAID The first one is irrelevant if the flex_bg option is used, since it already packs the bitmaps together and achieves the same effect. The second is meaningless for RAID-1 since

Andreas, why is it relevant only in case of RAID5 or RAID6? regards, Martin On Fri, Mar 7, 2014 at 5:57 PM, Andreas Dilger <adilger@dilger.ca> wrote: > Note that stride and stripe width only make sense for RAI-5/6 arrays. > For RAID-1 it doesn't really matter. > > Cheers, Andreas > >> On Mar 6, 2014, at 13:46, Martin T <m4rtntns@gmail.com> wrote: >>

...e merge to head, I'm just making sure I > got it right... The rest looks correct. > > + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, > + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, > + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, > > Does this mean that for floating point support in GHC, you need VFP registers? Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. The code in GHC is properly #ifdefed, so...

From: Matt Fleming <matt.fleming at linux.intel.com> This series fixes some bugs and switches the elflink branch to be entirely ELF modules. It applies on top of, http://syslinux.zytor.com/archives/2011-April/016369.html The deletions in the diff stat below are mainly from deleting com32/elflink/modules (finally!). Now there should be no duplicate code because we don't need COM32 and