search for: s19

...3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, im...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $sp, im...

Hi, I am trying to read the "credit.lisp" file of the Japanese credit database in UCI repository, but it is in lisp format which I do not know how to read. I have not found how to do that in the foreign library http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening <http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening> Could anyone help me? Best

...-1 5.36 1/3/2006 S7 -2 4.36 1/3/2006 S8 -3 3.574 1/3/2006 S9 -4 2.748 1/3/2006 S10 -5 1.933 1/3/2006 S11 -6 0.548 1/3/2006 S12 -7 -0.66 1/3/2006 S13 -8 -1.793 1/3/2006 S14 -9 -2.163 1/3/2006 S15 -10 -3.077 1/3/2006 S16 -11 -4.723 1/3/2006 S17 -12 -5.919 1/3/2006 S18 -13 -6.529 1/3/2006 S19 -14 -7.979 1/3/2006 S20 -15 -8.064 After making sure only positives are in for top 5 predictions and only negatives for the bottom 5 predictions 1/3/2006 S1 3 -1.943 1/3/2006 S20 4 10.376 1/3/2006 S3 2 8.611 1/3/2006 S4 1 7.465 1/3/2006 S16 -11 -4.723 1/3/2006 S17 -12 -5.919 1/3/2006 S18...

On Debian the Asterisk Makefile does /usr/sbin/update-rc.d asterisk start 10 2 3 4 5 . stop 91 2 3 4 5 .; which results in a /etc/rc2.d/S10asterisk being written. I think S10 is too early. bind9 : S15 mysql : S19 zaptel: S20 ntp : S23 What bothers me most is that mysql is not up when asterisk starts. That's a bad thing if there are #execs in your config files and if the scripts rely on mysql. So what about S50 or S95? Regards, Philipp Kempgen -- amooma GmbH - Bachstr. 126 - 56566 Neuwied - http...

...;t take my question as stopping the merge to head, I'm just making sure I got it right... The rest looks correct. + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, Does this mean that for floating point support in GHC, you need VFP registers? I don't know much how tablegen would work in this case, but I'd expect it to break during codegen (with a horrid error message) if you try to compile that to an ARMv4-ish core. Ma...

...2 6 S14 15 s 14 5 12 3 12 3 11 3 S15 16 s 7 2 11 3 5 2 10 2 S16 17 s 1 7 4 5 1 6 3 5 S17 18 s 6 2 7 4 6 2 7 4 S18 19 s 9 4 8 5 10 4 6 3 S19 20 s 8 2 6 5 9 2 6 4 S20 21 s 6 5 5 7 6 6 5 5 S21 22 s 8 8 3 7 6 7 5 3 S22 23 s 11 4 6 7 1 1 6 4 S23 24 s 6 3 2 4 6 4 2 2 S24 25 s...

Hello, first of all: one of the LLVM 3.0 new feature was a support for GHC specific calling convention on ARM platform. It looks like this support was merged just into 3.0 branch, specifically it appeared in 3.0 RC2. Anyway, I hope this is just a mistake or omission that such support was merged only into 3.0 and not also into HEAD. I've just found it by testing LLVM 3.1 with GHC 7.4.2 and

...t;), site = structure(c(1L, 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, 21L, 12L, 5L, 7L), group = structure(c(1L, 1L, 1L...

...quot;), site = structure(c(1L, 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, 21L, 12L, 5L, 7L), group = structure(c(1L, 1L, 1L, 2...

...> > 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, > > 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", > > "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", > > "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, > > 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, > > 21L, 12L, 5L, 7L), gro...

...> > 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, > > 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", > > "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", > > "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, > > 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, > > 21L, 12L, 5L, 7L), gro...

...05/2007 Randalstown 1 R1 FALSE 0 A 0 0 0 4 44 0 4 0 15.72 100 11/06/2007 Randalstown 1 R19 FALSE 0 A 0 0 0 0 2 0 0 7 15.20 101 30/06/2007 Somerset 0 S12 FALSE 0 A 0 0 0 0 0 0 1 7 14.04 102 03/07/2007 Somerset 0 S19 FALSE 0 A 0 0 0 0 0 0 0 3 15.00 103 29/05/2007 Tollymore 1 T11 FALSE 0 A 1 0 0 0 2 0 3 0 16.30 104 29/05/2007 Tollymore 1 T28 FALSE 0 A 0 0 0 0 0 0 0 0 14.49 And here is the syntax is used to run the ZINB with the error m...

...topping the merge to head, I'm just making sure I > got it right... The rest looks correct. > > + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, > + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, > + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, > > Does this mean that for floating point support in GHC, you need VFP registers? Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. The code in GHC is properly #if...