search for: s18

...B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $s...

If I'm understanding what's going on in this test correctly, what's happening is: * ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize * In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6) * The function has three arguments, so those three plus the register we need to hold the

...B %3:tgpr = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool) 96B $r0 = COPY %0:tgpr 112B $r1 = COPY %1:tgpr 128B $r2 = COPY %2:tgpr 144B tBLXr 14, $noreg, %3:tgpr, <regmask $lr $d8 $d9 $d10 $d11 $d12 $d13 $d14 $d15 $q4 $q5 $q6 $q7 $r4 $r5 $r6 $r7 $r8 $r9 $r10 $r11 $s16 $s17 $s18 $s19 $s20 $s21 $s22 $s23 $s24 $s25 $s26 $s27 and 35 more...>, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit $r2, implicit-def $sp 160B ADJCALLSTACKUP 0, 0, 14, $noreg, implicit-def dead $sp, implicit $sp 176B ADJCALLSTACKDOWN 0, 0, 14, $noreg, implicit-def dead $s...

Hi, I am trying to read the "credit.lisp" file of the Japanese credit database in UCI repository, but it is in lisp format which I do not know how to read. I have not found how to do that in the foreign library http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening <http://archive.ics.uci.edu/ml/datasets/Japanese+Credit+Screening> Could anyone help me? Best

...S5 0 1.648 1/3/2006 S6 -1 5.36 1/3/2006 S7 -2 4.36 1/3/2006 S8 -3 3.574 1/3/2006 S9 -4 2.748 1/3/2006 S10 -5 1.933 1/3/2006 S11 -6 0.548 1/3/2006 S12 -7 -0.66 1/3/2006 S13 -8 -1.793 1/3/2006 S14 -9 -2.163 1/3/2006 S15 -10 -3.077 1/3/2006 S16 -11 -4.723 1/3/2006 S17 -12 -5.919 1/3/2006 S18 -13 -6.529 1/3/2006 S19 -14 -7.979 1/3/2006 S20 -15 -8.064 After making sure only positives are in for top 5 predictions and only negatives for the bottom 5 predictions 1/3/2006 S1 3 -1.943 1/3/2006 S20 4 10.376 1/3/2006 S3 2 8.611 1/3/2006 S4 1 7.465 1/3/2006 S16 -11 -4.723 1/3/2006 S17...

...n't take my question as stopping the merge to head, I'm just making sure I got it right... The rest looks correct. + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, Does this mean that for floating point support in GHC, you need VFP registers? I don't know much how tablegen would work in this case, but I'd expect it to break during codegen (with a horrid error message) if you try to compile that to an ARMv4-ish core...

...0 8 S13 14 s 5 6 4 9 4 6 2 6 S14 15 s 14 5 12 3 12 3 11 3 S15 16 s 7 2 11 3 5 2 10 2 S16 17 s 1 7 4 5 1 6 3 5 S17 18 s 6 2 7 4 6 2 7 4 S18 19 s 9 4 8 5 10 4 6 3 S19 20 s 8 2 6 5 9 2 6 4 S20 21 s 6 5 5 7 6 6 5 5 S21 22 s 8 8 3 7 6 7 5 3 S22 23 s 11 4 6 7 1 1 6 4 S23 24 s...

...----------------------------------- #--------------------------------------------------------------------- # next to try in looking for faster solutions mayby: #require(sqldf) # centered moving average of length 7 #set.seed(1) #DF <- data.frame(x = rnorm(15, 1:15)) #s18 <- sqldf("select a.x x, avg(b.x) movavgx from DF a, DF b # where a.row_names - b.row_names between -3 and 3 # group by a.row_names having count(*) = 7 # order by a.row_names+0", # row.names = TRUE) #r18 <- data.frame(x = DF[4:12,], movavgx = rowMeans(embed(...

Hello, first of all: one of the LLVM 3.0 new feature was a support for GHC specific calling convention on ARM platform. It looks like this support was merged just into 3.0 branch, specifically it appeared in 3.0 RC2. Anyway, I hope this is just a mistake or omission that such support was merged only into 3.0 and not also into HEAD. I've just found it by testing LLVM 3.1 with GHC 7.4.2 and

..."factor"), site = structure(c(1L, 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, 21L, 12L, 5L, 7L), group = struc...

...s = "factor"), site = structure(c(1L, 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, 21L, 12L, 5L, 7L), group = structur...

...pinpoint it more if I am missing some DLLs? Or is there a way to determine that the DLLs are installed, but need to be modified slightly to work? As a side note, if I try to install the MDAC_TYP.EXE (for MDAC) that I downloaded from Microsoft through Wine, I get this as a response: [Image: http://s18.postimage.org/fyilb9gpj/Screen_shot_2012_03_30_at_3_17_27_PM.png ] Can I assume that even though a direct Wine install doesn't work, that winetricks did work since obdc32 and obdccp32?

...= structure(c(1L, > > 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, > > 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", > > "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", > > "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, > > 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, > > 21L,...

...; structure(c(1L, > > 12L, 13L, 14L, 15L, 16L, 17L, 18L, 19L, 2L, 3L, 4L, 5L, 6L, 7L, > > 8L, 9L, 10L, 11L), .Label = c("s1", "s10", "s11", "s12", "s13", > > "s14", "s15", "s16", "s17", "s18", "s19", "s2", "s3", "s4", "s5", > > "s6", "s7", "s8", "s9"), class = "factor"), temp = c(23L, 21L, > > 10L, 15L, 16L, 8L, 13L, 1L, 23L, 19L, 25L, 19L, 12L, 16L, 19L, > > 21L,...

...can manually run them from windows shell or by double clicking them. They just won't run by themselves. I have done the registry pokes + policy changes as: https://community.spiceworks.com/topic/1389891-windows-10-and-sysvol-netlogon https://support.microsoft.com/en-us/kb/2895815 https://s18.postimg.org/643ketg49/regedit_samba.png https://s22.postimg.org/6awshoi8h/network_samba.png https://s16.postimg.org/aul5oxh91/grouppolicy_samba.png everything appears to work just no execution of script automatically. I have made sure they are windows line ending format (via unix2dos). te...

...as stopping the merge to head, I'm just making sure I > got it right... The rest looks correct. > > + CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>, > + CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>, > + CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>, > > Does this mean that for floating point support in GHC, you need VFP registers? Yes and no. Shortly: original GHC/ARM/LLVM port was done by Stephen on ARMv5/Qemu IIRC. I've later added whole VFP support and ARMv7 support. The code in GHC is properl...

Hello list. I'm trying to rebuild the 2.6.9.67.0.20.EL kernel, but it fails even without modifications. How did I try it? Created a (non-root) build environment (not a mock ) Installed the kernel.scr.rpm and did a rpmbuild -ba --target=`uname -m` kernel-2.6.spec 2> prep-err.log | tee prep-out.log The build failed at the end: Processing files: kernel-xenU-devel-2.6.9-67.0.20.EL Checking