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...t, $addr0", [(set CPURegs:$dst, > (add (MipsHi tglobaladdr:$addr0), (MipsLo > tglobaladdr:$addr1)))], IIAlu>; > > Note that you still need to find a way to print "g1" instead of "%hi(g1)". > > On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > > Hi, > > In order to emit "la $4,ADDR" instead of lui followed by addiu to > load > > the data address, could you advise what is proper way to revise td files > in > > the MIPS target? > > Thanks, > &gt...

...llc target for SimpleScalar PISA architecture. On Fri, Oct 7, 2011 at 2:41 PM, Jim Grosbach <grosbach at apple.com> wrote: > I reiterate. You should fix the simulator. It is broken. The compiler is > not. Fix what's broken. > > -Jim > > On Oct 7, 2011, at 1:11 PM, Gang-Ryung Uh wrote: > > > Hi, > > > > I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. > I wonder whether I can use this. If does, I wonder what would be the right > way to use. Thanks, > > > > > > > > On Thu, Oct 6, 2011 at 11:29...

I reiterate. You should fix the simulator. It is broken. The compiler is not. Fix what's broken. -Jim On Oct 7, 2011, at 1:11 PM, Gang-Ryung Uh wrote: > Hi, > > I noticed one class in MipsInstrFormats.td:L46 -> Class MipsPseudo. I wonder whether I can use this. If does, I wonder what would be the right way to use. Thanks, > > > > On Thu, Oct 6, 2011 at 11:29 AM, Akira Hatanaka <ahatanak at gmail.com...

Hi, In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Thanks, -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/l...

...with binutils 1.5.2, and the ld fails at "lui" (bfd error). However, the ld is happy with "la" (assembler macro) and simulator correctly simulates. On Wed, Oct 5, 2011 at 5:04 PM, Eric Christopher <echristo at apple.com> wrote: > > On Oct 5, 2011, at 4:01 PM, Gang-Ryung Uh wrote: > > > Hi, > > > > In order to emit "la $4,ADDR" instead of lui followed by addiu to > load the data address, could you advise what is proper way to revise td > files in the MIPS target? > > Why? > > -eric > > -- Gang-Ryung Uh,...

...:$addr1), "la $dst, $addr0", [(set CPURegs:$dst, (add (MipsHi tglobaladdr:$addr0), (MipsLo tglobaladdr:$addr1)))], IIAlu>; Note that you still need to find a way to print "g1" instead of "%hi(g1)". On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > Hi, >      In order to emit "la $4,ADDR" instead of lui followed by addiu to load > the data address, could you advise what is proper way to revise td files in > the MIPS target? > Thanks, > > -- > Gang-Ryung Uh, Associate...

...s > redundant) > > If you do not specify the target cpu with -mcpu, by default it will > generate code for Mips1, which has not been tested as thoroughly as Mips32r2 > (-mcpu=4ke) or Mips2 (-mcpu=mips2). > > The default ABI is o32. > > On Sat, Jul 9, 2011 at 8:32 AM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > >> We are trying to use LLVM (Clang as the C frontend) to generate code for >> 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 >> sslittle-na-sstrix platform. Can you advise what would be the right way to >> use th...

On Jul 15, 2011, at 10:13 AM, Gang-Ryung Uh wrote: > Hi, > > We have tried and generate assembly code for very simple test C code. But, binutils-2.5.2 (simplesim-3.0) cannot handle the produced assembly code with the following complaints. Could you advise which version of bitutils that we need to use for mips code with LLVM...

...nately, this particular version of binutils doesn't seem to handle global-offset-table (position independent code) and the some of the mips instructions. Thanks, On Fri, Jul 15, 2011 at 11:39 AM, Eric Christopher <echristo at apple.com>wrote: > > On Jul 15, 2011, at 10:13 AM, Gang-Ryung Uh wrote: > > > Hi, > > > > We have tried and generate assembly code for very simple test C code. > But, binutils-2.5.2 (simplesim-3.0) cannot handle the produced assembly code > with the following complaints. Could you advise which version of bitutils > that we ne...

Hi, I wonder whether there is any good way to build etags table for LLVM src. Thanks, Gang-Ryung Uh, -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20110725/632ec1f0/attachment.html>

On Oct 5, 2011, at 4:01 PM, Gang-Ryung Uh wrote: > Hi, > > In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Why? -eric

...u=4ke foo.ll -o foo.s (the -march option is redundant) If you do not specify the target cpu with -mcpu, by default it will generate code for Mips1, which has not been tested as thoroughly as Mips32r2 (-mcpu=4ke) or Mips2 (-mcpu=mips2). The default ABI is o32. On Sat, Jul 9, 2011 at 8:32 AM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > We are trying to use LLVM (Clang as the C frontend) to generate code for > 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 > sslittle-na-sstrix platform. Can you advise what would be the right way to > use the LLVM compiler infr...

We are trying to use LLVM (Clang as the C frontend) to generate code for 32-bit MIPS (little-endian)l, which can run on simplescalar 3.0 sslittle-na-sstrix platform. Can you advise what would be the right way to use the LLVM compiler infrastructure? The following is the one I used, but it appears that it produce the code in big-endian (and I wonder whether the calling convention is right.) To

...s cch(Surv(edrel, rel) ~ stage + histol + age, data =ccoh.data, subcoh = ~subcohort, id=~seqno, cohort.size=4028, method="SelfPren") cch(Surv(edrel, rel) ~ stage + histol + age, data =ccoh.data, subcoh = ~subcohort, id=~seqno, cohort.size=4028, method="LinYing") Ryung Kim Department of Epidemiology and Population Health Albert Einstein College of Medicine [[alternative HTML version deleted]]

I tried llc with -mcpu=help and it dosn't list Sparc. Thanks. --Gang On Tue, Mar 16, 2010 at 12:43 PM, Sergey Yakoushkin < sergey.yakoushkin at gmail.com> wrote: > Hi, > > Target architecture for llc can be specified using -march, -mcpu, > -mattr options. > > Is it possible to override target CPU attributes when using llvm-gcc > compiler? > > Regards, >

...1.5. We expect that it can be quite difficult to make simplescalar use the current gnu binutils. Instead, we are thinking of modifing llc to generate mips code for binutils-1.5. Having said this, could you advise which module(s) in LLVM we need to modify? Thanks in advance. Regards, -- -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/l...

...person managing the list at llvmdev-owner at cs.uiuc.edu When replying, please edit your Subject line so it is more specific than "Re: Contents of LLVMdev digest..." Today's Topics: 1. Re: LLVM IR is a compiler IR (David A. Greene) 2. MIPS 32bit code generation (Gang-Ryung Uh) 3. Re: MIPS 32bit code generation (Eric Christopher) 4. TableGen and Greenspun (Jakob Stoklund Olesen) 5. Re: MIPS 32bit code generation (Gang-Ryung Uh) 6. Re: replacing a global variable by a constant (neda 8664) 7. Re: replacing a global variable by a constant (Duncan Sands)...

*What would be the recommended way to debug LLVM opt pass? Is there any way to perform source level debugging on a particular opt pass? * *-- UGR* -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20100110/e250208a/attachment.html>

Hi Gang-Ryung! Your reverse iteration of instructions in the BB > * for (BasicBlock::iterator II = BB->end(); II != BB->begin(); ) *{ > > Instruction &I = *--II; > > if (isLoopInvariantInst(I) && canSinkOrHoistInst(I) && >...

Hi, Target architecture for llc can be specified using -march, -mcpu, -mattr options. Is it possible to override target CPU attributes when using llvm-gcc compiler? Regards, Sergey Y.