Displaying 20 results from an estimated 43 matches for "rt2".
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2017 Oct 11
1
[PATCH v1 01/27] x86/crypto: Adapt assembly for PIE support
...tunpack_blocks(RA2, RB2, RC2, RD2, RTMP, RX, RKRF, RKM);
diff --git a/arch/x86/crypto/des3_ede-asm_64.S b/arch/x86/crypto/des3_ede-asm_64.S
index 8e49ce117494..4bbd3ec78df5 100644
--- a/arch/x86/crypto/des3_ede-asm_64.S
+++ b/arch/x86/crypto/des3_ede-asm_64.S
@@ -138,21 +138,29 @@
movzbl RW0bl, RT2d; \
movzbl RW0bh, RT3d; \
shrq $16, RW0; \
- movq s8(, RT0, 8), RT0; \
- xorq s6(, RT1, 8), to; \
+ leaq s8(%rip), RW1; \
+ movq (RW1, RT0, 8), RT0; \
+ leaq s6(%rip), RW1; \
+ xorq (RW1, RT1, 8), to; \
movzbl RW0bl, RL1d; \
movzbl RW0bh, RT1d; \
shrl $16, RW0d; \
- xorq s4(, RT2, 8), RT0...
2010 Jul 23
2
ZFS volume turned into a socket - any way to restore data?
...cd rt
bash: cd: rt: Not a directory
# cat rt
cat: rt: Operation not supported on transport endpoint
a# zfs list
NAME USED AVAIL REFER MOUNTPOINT
data 992G 828G 47.8K /volumes/data
...
data/rt 800G 828G 800G /volumes/data/rt
data/rt2 0 828G 800G /volumes/data/rt2
syspool 6.31G 23.0G 35.5K legacy
syspool/dump 2.79G 23.0G 2.79G -
syspool/rootfs-nmu-000 115M 23.0G 1.32G legacy
syspool/rootfs-nmu-001 1.59G 23.0G 1.17G legacy
syspool/rootfs-nmu-002 793M 23.0G 1.17...
2008 Nov 17
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...annel of R3.
It's complicate.
Imagine a non-existed temp register named 'Rt1', the content of its
'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
and imagine another non-existed temp register named 'Rt2', the content of
its 'a','b','c','d' channel are got from 'b','b','a','a' channel of R2.
and then add Rt1 & Rt2, put the result to R3
this means
the 'a' channel of R3 will be equal to the 'a' channel of Rt1 plus...
2008 Nov 20
4
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...e.
> > Imagine a non-existed temp register named 'Rt1', the content of its
> > 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
> > and imagine another non-existed temp register named 'Rt2', the
> > content of its 'a','b','c','d' channel are got from 'b','b','a','a'
> > channel of R2.
> > and then add Rt1 & Rt2, put the result to R3
> > this means
> > the 'a' channel of R...
2008 Nov 18
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...#39;s complicate.
> Imagine a non-existed temp register named 'Rt1', the content of its
> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
> and imagine another non-existed temp register named 'Rt2', the
> content of its 'a','b','c','d' channel are got from 'b','b','a','a'
> channel of R2.
> and then add Rt1 & Rt2, put the result to R3
> this means
> the 'a' channel of R3 will be equal to the ...
2005 Jun 29
0
Upload shaper problem
Hello guys,
I am experiencing a strange behaviour with HTB. Here is my situation:
Test PC -------- internet ------------- ISP ----- fiber connection ---------
(eht2) RT1 (eth1) --------- wireless connection ------------ (eth4) RT2
(eth0) -------- users
RT1 - Slackware router
RT2 - Slackware router
Delay between Test PC and ISP is approx 450 ms.
I have the following shapers
RT1 ETH2 - dedicated bandwidth for Test PC 40kbps
RT2 ETH4 - dedicated bandwidth for Test PC 30kbps
RT2 ETH4 - dedicated bandwidth for...
2008 Nov 21
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...>> Imagine a non-existed temp register named 'Rt1', the content of its
>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
>>> and imagine another non-existed temp register named 'Rt2', the
>>> content of its 'a','b','c','d' channel are got from 'b','b','a','a'
>>> channel of R2.
>>> and then add Rt1 & Rt2, put the result to R3
>>> this means
>>> the 'a' c...
2008 Nov 20
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...>> Imagine a non-existed temp register named 'Rt1', the content of its
>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
>>> and imagine another non-existed temp register named 'Rt2', the
>>> content of its 'a','b','c','d' channel are got from 'b','b','a','a'
>>> channel of R2.
>>> and then add Rt1 & Rt2, put the result to R3
>>> this means
>>> the 'a' c...
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...magine a non-existed temp register named 'Rt1', the content of its
> >>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
> >>> and imagine another non-existed temp register named 'Rt2', the
> >>> content of its 'a','b','c','d' channel are got from 'b','b','a','a'
> >>> channel of R2.
> >>> and then add Rt1 & Rt2, put the result to R3
> >>> this means
> >&...
2004 Jun 02
0
how to route based on link load?
...bnet 2 |
+----------+ +------+ +------+ +----------+
\ /
\ +------+ /
\| rt 3 |/
+------+
the bandwidth of the links is as follows:
sn1 - rt1 100mbit
sn2 - rt2 100mbit
rt1 - rt2 - rt3 10mbit
now there are multiple flows from sn1 to sn2.
if the load on the prefered link (rt1-rt2) is 80% or more
i want to utilisize the rt1-rt3-rt2 route as well.
but only in this case - not normaly.
so i think ecmp with weights is not the solution to this....
2008 Nov 22
2
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...magine a non-existed temp register named 'Rt1', the content of its
> >>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of R1,
> >>> and imagine another non-existed temp register named 'Rt2', the
> >>> content of its 'a','b','c','d' channel are got from 'b','b','a','a'
> >>> channel of R2.
> >>> and then add Rt1 & Rt2, put the result to R3
> >>> this means
> >&...
2003 Dec 29
1
Agent setup
Dear Group,
I have been successful in setting up the Agents, queues and getting agents
to log in.
Is there a way that I could configure the system so that the agent is called
back. i.e. the agent logs into the system, a call is destined for them and
their phone rings.
If some one has this setup I would be very interested in hearing from them.
Warm Regards and Thanks
---------------
Shad
2008 Nov 24
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...9;, the content of
>>>>> its
>>>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of
>>>>> R1,
>>>>> and imagine another non-existed temp register named 'Rt2', the
>>>>> content of its 'a','b','c','d' channel are got from
>>>>> 'b','b','a','a'
>>>>> channel of R2.
>>>>> and then add Rt1 & Rt2, put the result to R3
>>...
2018 Mar 13
32
[PATCH v2 00/27] x86: PIE support and option to extend KASLR randomization
Changes:
- patch v2:
- Adapt patch to work post KPTI and compiler changes
- Redo all performance testing with latest configs and compilers
- Simplify mov macro on PIE (MOVABS now)
- Reduce GOT footprint
- patch v1:
- Simplify ftrace implementation.
- Use gcc mstack-protector-guard-reg=%gs with PIE when possible.
- rfc v3:
- Use --emit-relocs instead of -pie to reduce
2018 Mar 13
32
[PATCH v2 00/27] x86: PIE support and option to extend KASLR randomization
Changes:
- patch v2:
- Adapt patch to work post KPTI and compiler changes
- Redo all performance testing with latest configs and compilers
- Simplify mov macro on PIE (MOVABS now)
- Reduce GOT footprint
- patch v1:
- Simplify ftrace implementation.
- Use gcc mstack-protector-guard-reg=%gs with PIE when possible.
- rfc v3:
- Use --emit-relocs instead of -pie to reduce
2017 Oct 04
28
x86: PIE support and option to extend KASLR randomization
These patches make the changes necessary to build the kernel as Position
Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below
the top 2G of the virtual address space. It allows to optionally extend the
KASLR randomization range from 1G to 3G.
Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler
changes, PIE support and KASLR in general. Thanks to
2017 Oct 04
28
x86: PIE support and option to extend KASLR randomization
These patches make the changes necessary to build the kernel as Position
Independent Executable (PIE) on x86_64. A PIE kernel can be relocated below
the top 2G of the virtual address space. It allows to optionally extend the
KASLR randomization range from 1G to 3G.
Thanks a lot to Ard Biesheuvel & Kees Cook on their feedback on compiler
changes, PIE support and KASLR in general. Thanks to
2008 Nov 22
0
[LLVMdev] Does current LLVM target-independent code generator supports my strange chip?
...9;, the content of
>>>>> its
>>>>> 'a','b','c','d' channel are got from 'a','b','a','b' channel of
>>>>> R1,
>>>>> and imagine another non-existed temp register named 'Rt2', the
>>>>> content of its 'a','b','c','d' channel are got from
>>>>> 'b','b','a','a'
>>>>> channel of R2.
>>>>> and then add Rt1 & Rt2, put the result to R3
>>...
2018 May 23
33
[PATCH v3 00/27] x86: PIE support and option to extend KASLR randomization
Changes:
- patch v3:
- Update on message to describe longer term PIE goal.
- Minor change on ftrace if condition.
- Changed code using xchgq.
- patch v2:
- Adapt patch to work post KPTI and compiler changes
- Redo all performance testing with latest configs and compilers
- Simplify mov macro on PIE (MOVABS now)
- Reduce GOT footprint
- patch v1:
- Simplify ftrace
2005 Feb 23
1
error when trying access internet.
...55.0
NETWORK=200.138.174.0
ONBOOT=yes
TYPE=Ethernet
[root at cedaspy network-scripts]# route
Tabela de Roteamento IP do Kernel
Destino Roteador MascaraGen. Opcoes Metrica Ref Uso Iface
200.138.174.0 * 255.255.255.0 U 0 0 0 eth0
default rt2.voe.com.br 0.0.0.0 UG 0 0 0 eth0
[root at cedaspy network-scripts]# ifconfig
eth0 Encapsulamento do Link: Ethernet Endereco de HW 00:0E:A6:CD:95:AD
inet end.: 200.138.174.27 Bcast:200.138.174.255 Masc:255.255.255.0
UP BROADCASTRUNNING MULTICAST...